Capacitor array structure and manufacture method thereof

Abstract

The invention provides a capacitor array structure and a manufacture method thereof. The method includes 1) providing a semiconductor substrate; 2) forming sacrificial layer and support layers in an alternating and stacking manner on the upper surface of the semiconductor substrate; 3) forming graphic mask layers on the upper surfaces of the sacrificial layer and support layers arranged in an alternating and stacking manner, wherein the graphic mask layers have a plurality of holes; 4) forming capacitance holes in the support layers and the sacrificial layers; 5) forming lower electrode layersin the capacitance layers; 6) removing the sacrificial layers and remaining the support layers on the semiconductor substrate; 7) forming capacitance medium layers on the inner surfaces and the outersurface of the lower electrode layers; 8) forming upper electrode layers on the outer surfaces of the capacitance medium layers; 9) forming upper electrode filling layers on the outer surface of theupper electrode layers, wherein the material of the upper electrode filling layers contains boron doped germanium-silicon. According to the invention, temperature of a formation technique can be reduced, so that influence on the capacitance medium layers by thermal budge can be reduced. At the same time, current carrier moving rate can be improved, so that the resistance value of the filling layers can be reduced.

Description

Technical field [0001] The invention belongs to the field of semiconductor devices and manufacturing, and particularly relates to a capacitor array structure and a manufacturing method thereof. Background technique [0002] Dynamic random access memory (Dynamic Random Access Memory, referred to as: DRAM) is a semiconductor storage device commonly used in computers, which is composed of many repeated storage units. In the DRAM manufacturing process below 20nm, DRAM adopts a stacked capacitor structure. The capacitor is a vertical cylindrical shape with a high aspect ratio to increase the surface area. Therefore, it must include the lower electrode layer, the capacitor dielectric layer and the upper electrode layer. The capacitor gap of the electrode layer is filled with a filling layer to stabilize the capacitor structure. [0003] Since the capacitor dielectric layer of the capacitor is greatly affected by the thermal budget, if the filling layer uses a high-temperature process, t...

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Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a capacitor array structure and its manufacturing method, which is used to solve the problem of excessive crystallization of the capacitor dielectric layer caused by the high process temperature of the filling layer in the prior art The problem of leakage current caused by the increase of its conductivity, and the excessively fast deposition speed of the use of boron-doped polysilicon as the filling layer makes the filling layer of the upper electrode sealed early, and bubbles are formed inside, thereby affecting its performance. question

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