Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Multi-bit memory of semiconductor nano-array organic field-effect transistor and preparation method thereof

A field-effect transistor and nano-array technology, applied in the field of semiconductor nano-array organic field-effect transistor multi-bit memory and its preparation, can solve the problems of poor data stability, slow light response speed, difficult multi-level storage and the like, and achieve high response speed , the effect of low operating voltage and high storage density

Inactive Publication Date: 2018-07-06
NANJING UNIV OF POSTS & TELECOMM
View PDF6 Cites 9 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Judging from the current overall research progress at home and abroad, OFETM still faces the following challenges: (1) The current research is still mainly focused on the storage phenomenon and storage behavior of OFETM. There are few studies on storage; (2) The operating voltage is too high (>100 V), the photoresponse speed is too slow (incident light >1s), the storage density is low (difficult to achieve multi-level storage), and the light-dark current ratio is low (< 100), Poor data stability (maintenance time <105 s); (3) The mechanism of electrical storage needs to be further elucidated and systematically explored

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multi-bit memory of semiconductor nano-array organic field-effect transistor and preparation method thereof
  • Multi-bit memory of semiconductor nano-array organic field-effect transistor and preparation method thereof
  • Multi-bit memory of semiconductor nano-array organic field-effect transistor and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0035] This embodiment provides an organic field effect transistor memory structure, the schematic diagram of which is as follows figure 1 shown, including:

[0036] substrate;

[0037] a gate electrode formed over the substrate;

[0038] a gate insulating layer covering the gate electrode;

[0039] a polymer film layer of a semiconductor nanoarray formed on the gate insulating layer;

[0040] an organic semiconductor layer formed on the semiconductor nanoarray thin film layer;

[0041] The source and drain electrodes are formed on both sides of the channel region on the surface of the organic semiconductor layer.

[0042] The substrate is a highly doped silicon wafer or a glass wafer or plastic PET.

[0043] In the technical solution of this embodiment, heavily doped silicon is used as the substrate and gate electrode; a layer of 50-300nm silicon dioxide is used as the gate insulating layer; the semiconductor nano-array is formed by mixed spin coating of polymer and semi...

Embodiment 2

[0058] In the technical solution of this embodiment, heavily doped silicon is used as the substrate and gate electrode; a layer of 50-300 nm silicon dioxide is used as the gate insulating layer; the polymer film layer doped with semiconductor nanoparticles is made of polymer polymethyl Methyl acrylate (PMMA), semiconducting nanoparticles made of C 60 Preparation, the thickness after doping is 15-20 nm; a layer of 30-50 nm thick pentacene is vapor-deposited on the gate insulating layer to serve as an organic semiconductor layer; and metal copper is vapor-deposited on both sides of the conductive channel as source-drain electrodes.

[0059] (1) Prepare polymethyl methacrylate (PMMA) solution and C 60 solutions, the solution concentrations were 4 mg / mL and 0.6 mg / mL, respectively, and the solvent was toluene without additional treatment;

[0060] (2) Mix the solutions PS and C prepared in (1) 60 Mix at a ratio of 1:1 and sonicate for 30 minutes at a frequency of 100KHz;

[006...

Embodiment 3

[0066] In the technical solution of this embodiment, heavily doped silicon is used as the substrate and gate electrode; a layer of 50-300 nm silicon dioxide is used as the gate insulating layer; the polymer film layer doped with semiconductor nanoparticles is made of polymer polyethylene Carbazole (PVK), semiconducting nanoparticles composed of C 60 Preparation, the thickness after doping is 15-20 nm; a layer of pentacene with a thickness of 30-50 nm is vapor-deposited on the gate insulating layer to serve as an organic semiconductor layer; and metal copper is vapor-deposited on both sides of the conductive channel as source-drain electrodes.

[0067] (1) Prepare polyvinylcarbazole (PVK) solution and C 60 solutions, the solution concentrations were 4 mg / mL and 0.6 mg / mL, respectively, and the solvent was toluene without additional treatment;

[0068] (2) Mix the solutions PS and C prepared in (1) 60 Mix at a ratio of 1:1 and sonicate for 30 minutes at a frequency of 100KHz; ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention provides a multi-bit memory of a semiconductor nano-array organic field-effect transistor and a preparation method thereof. The memory is composed of a substrate, a gate insulating layer, a charge storage layer, an organic semiconductor layer, and a source electrode and drain electrode that are arranged successively from bottom to top. The charge storage layer is a semiconductor nano-array film prepared by a low-dielectric-constant polymer film doped with semiconductor nanoparticles. In addition, according to the preparation method, a substrate doped with silicon heavily is coated and doped with a low-dielectric-constant polymer solution doped with semiconductor nanoparticles and then an organic semiconductor layer and source and drain electrodes are plated by means of vapordeposition to make a memory. According to the invention, the polymer is doped with the semiconductor nanoparticles and annealing is carried out to form the memory density of the nano-array optimized device; the multi-bit storage of the single device is formed, so that the switching speed and the storage stability are enhanced substantially. Moreover, the transistor is prepared by using a solutionmethod mainly, so that the cost is low and the transistor is easy to promote.

Description

technical field [0001] The invention belongs to the technical field of memory in the semiconductor industry, and in particular relates to a semiconductor nano-array organic field effect transistor multi-bit memory and a preparation method thereof. Background technique [0002] As the basic components in circuits, organic field effect transistors are in line with the future development direction of the wearable electronics industry due to their wide range of material sources, gentle processing methods, and easy large-scale mass production. At the same time, the structure of the organic field effect transistor determines that it has very rich functional applications, such as light-emitting products, storage devices, sensors, switches, etc., so it has a very broad application prospect in the field of information electronics in the future. [0003] As a multifunctional device, Organic Field-effect Transistor Memory (OFETM) can be used in new display elements, storage elements or...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L51/05H01L51/30H01L51/40
CPCH10K85/114H10K85/141H10K10/486H10K10/488H10K10/491H10K10/466
Inventor 仪明东陈旭东黄维宋子忆解令海
Owner NANJING UNIV OF POSTS & TELECOMM
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com