Metal gate, semiconductor device and manufacturing method thereof
A technology of metal gates and manufacturing methods, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems affecting the yield and failure of integrated circuit products, achieve good gap filling ability, improve yield, The effect of good process control
Active Publication Date: 2021-04-02
SEMICON MFG INT TIANJIN +1
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Problems solved by technology
However, in actual production, it is found that HKMG SRAM products often encounter failures during MBIST (memory built-in self-test), and the hit rate of batch failures is close to 100%, which obviously seriously affects the yield of integrated circuit products
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[0038] Please refer to Figure 1A , a process of forming a metal gate of a pull-down transistor (PD NFET) of a 28nm static memory (SRAM) using a gate-last (Gate-last) process includes:
[0039] Firstly, a semiconductor substrate (such as bulk silicon) 100 is provided, on which a replacement gate structure (not shown) is formed, and an interlayer covering the replacement gate structure is located on the semiconductor substrate 100 medium layer 101;
[0040] Next, using the replacement gate structure as a stop layer, chemical mechanical polishing (CMP) is performed on the interlayer dielectric layer 101 until the surface of the replacement gate structure is exposed;
[0041] Then, removing the replacement gate structure, forming a gate opening in the interlayer dielectric layer 101;
[0042] Next, hafnium oxide (HfO 2 ) layer 102, titanium nitride (TiN) layer 103, tantalum nitride (TaN) layer 104, titanium aluminum (TiAl) layer 105, TiN layer 106, Ti layer 107 and Al layer 108...
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A metal gate, semiconductor device and manufacturing method thereof are provided. Among a metal barrier layer, and a work function setting metal layer, at least one of the upper surface layers is an oxygen-enriched layer, and the oxygen in the oxygen-enriched layer reacts with the electrode metal in the metal electrode layer to form an oxidization layer to block the diffusion of the electrode metal in the metal electrode layer to the semiconductor substrate, thereby improving device reliability, reducing the device failure rate, and improving the yield of integrated circuit products; and further, by depositing a relatively thick covering barrier layer using the Extensa deposition system, good control of the covering barrier layer deposition process can be achieved, so that the subsequent metal electrode layer has a good gap filling capability and further blocks the electrode metal in the metal electrode layer from diffusing toward the semiconductor substrate.
Description
technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a metal gate, a semiconductor device and a manufacturing method thereof. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is getting smaller and smaller, and the gate stack structure of high-K gate dielectric layer and metal gate (abbreviated as high-K metal gate, abbreviated as HKMG) is adopted. Introduced into MOS transistors, such as the pull-down transistor (PD NFET) of static memory (SRAM) at the 28nm node, to reduce the parasitic capacitance of the gate of the MOS transistor and increase the speed of the device. However, it is found in actual production that HKMG SRAM products often encounter failures during MBIST (memory built-in self-test), and the hit rate of batch failures is close to 100%, which obviously seriously affects the yield of integrated ci...
Claims
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IPC IPC(8): H01L21/28H01L29/423H01L29/49
CPCH01L21/28008H01L29/42372H01L29/495
Inventor 江涛
Owner SEMICON MFG INT TIANJIN