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An enhanced hemt device with a p-type buried layer structure and its preparation method

An enhanced, layer-structured technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to solve problems such as reduced channel electron mobility, reduced device reliability, and increased device on-resistance

Active Publication Date: 2021-09-14
DALIAN UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, these methods have some unavoidable defects: the surface unevenness caused by barrier layer etching will enhance the impurity scattering of electrons in the channel, resulting in a decrease in channel electron mobility and degradation of on-state resistance; the injection barrier layer The fluorine ions in the fluorine ion have temperature instability, so the threshold voltage drifts with temperature, which reduces the reliability of the device; the insertion of the P-GaN cap layer increases the distance between the gate and the channel, which weakens the gate control ability of the device , leading to the degradation of the device transconductance, thereby reducing the switching rate of the device
Since the above three methods all perform additional process steps on the gate barrier layer above the channel, additional defects and impurities are introduced, so the conductivity of the two-dimensional electron gas channel is degraded, and the on-resistance of the device is increased.

Method used

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  • An enhanced hemt device with a p-type buried layer structure and its preparation method
  • An enhanced hemt device with a p-type buried layer structure and its preparation method
  • An enhanced hemt device with a p-type buried layer structure and its preparation method

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Embodiment 1

[0042]An enhanced HEMT device with a P-type buried layer structure, the basic components of the device structure are as follows from bottom to top:

[0043] (1) Material substrates such as Si, sapphire, SiC, GaN, diamond or graphene, due to the different lattice constants, thermal expansion coefficients and thermal conductivity of different materials, can be selected according to the cost and the quality requirements of the epitaxial wafer;

[0044] (2) A buffer layer made of AlN or AlGaN superlattice structure;

[0045] (3) An unintentionally doped i-GaN drift layer of 0.5-10 μm;

[0046] (4) The P-GaN buried layer located in the i-GaN drift layer is used to deplete the electrons in the 2-DEG channel below the gate under zero bias gate voltage to achieve enhanced operation;

[0047] (5) An AlGaN barrier layer with an Al composition of 0.1 to 0.35 above the i-GaN channel layer to form a conductive 2-DEG in the i-GaN channel layer;

[0048] (6) The gate passivation layer is u...

Embodiment 2

[0052] Step ①: wafer growth. Using semiconductor material growth technologies such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE) to sequentially grow AlN or AlGaN superlattice structure buffer layers on Si, sapphire or GaN substrates, 0.5-10μm unintentional Doped i-GaN layers, such as image 3 shown;

[0053] Step ②: hard mask growth. Deposition of SiO by plasma-enhanced chemical vapor deposition (PECVD) or electron beam evaporation 2 、Si 3 N 4 Or Ni metal as a hard mask layer, and use semiconductor photolithography technology to achieve a mask opening of 1-3 μm, such as Figure 4 shown. Among them, the semiconductor photolithography technology includes a complete set of steps such as uniform coating, soft baking, exposure, development, and film hardening;

[0054] Step ③: Etching the groove of the buried layer. Use semiconductor etching technology to make the groove required for growing the buried layer, and etch the groove with a...

Embodiment 3

[0059] Step ①: wafer growth. Similar to step 1 of embodiment 2;

[0060] Step ②: hard mask growth. Similar to step 2 of embodiment 2;

[0061] Step ③: ion implantation. Use ion implantation technology to implant Mg or Fe or Mg / Al composite impurities on the surface of the sample, then remove the hard mask with buffered hydrofluoric acid BOE solution to obtain a flat GaN surface, and use thermal annealing technology to activate impurities to complete P-GaN Buried layer fabrication, such as Figure 9 shown;

[0062] Step ④: Heterojunction and passivation layer growth. Similar to step 5 of embodiment 2;

[0063] Step ⑤: fabrication of source, drain and gate electrodes. Similar to step 6 of embodiment 2.

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Abstract

An enhanced HEMT device with a P-type buried layer structure and a preparation method thereof belong to the field of semiconductor transistor device manufacture. The technical points include: sequentially growing a buffer layer, an i-GaN drift layer, a barrier layer and a gate passivation layer on a semiconductor substrate, the i-GaN drift layer is provided with a source electrode and a drain electrode, and the gate A gate electrode is arranged on the passivation layer, and a P-type buried layer is embedded in the i-GaN drift layer. This structure uses the P-type buried layer to form a PN junction built-in electric field, thereby depleting the two-dimensional electron gas under the gate to achieve the purpose of enhancement. The beneficial effects are: the enhanced HEMT device with a P-type buried layer structure and the preparation method thereof according to the present invention can simultaneously improve the stable and uniform positive direction of the device without degrading the conductivity of the two-dimensional electron gas channel. Threshold voltage is an important technical supplement to this field.

Description

technical field [0001] The invention belongs to the field of manufacturing semiconductor transistor devices, in particular to an enhanced HEMT device with a P-type buried layer structure and a preparation method thereof. Background technique [0002] Since the end of the 20th century, after the first generation of semiconductors represented by Si and the second generation of semiconductors represented by GaAs, the third generation of semiconductor materials has developed rapidly. The third-generation semiconductor materials have excellent physical and chemical properties, and have been widely used in wireless communications, satellites, lighting and other fields in recent years. The more representative materials are GaN and SiC. The third-generation semiconductor is also called a wide bandgap semiconductor, which has a wider bandgap, generally greater than 2eV, a higher breakdown field strength, a higher thermal conductivity and a higher electron saturation rate, so it has ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/778H01L21/336H01L29/06
CPCH01L29/0607H01L29/66462H01L29/778
Inventor 黄火林李飞雨陶鹏程孙仲豪曹亚庆
Owner DALIAN UNIV OF TECH