An enhanced hemt device with a p-type buried layer structure and its preparation method
An enhanced, layer-structured technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to solve problems such as reduced channel electron mobility, reduced device reliability, and increased device on-resistance
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Embodiment 1
[0042]An enhanced HEMT device with a P-type buried layer structure, the basic components of the device structure are as follows from bottom to top:
[0043] (1) Material substrates such as Si, sapphire, SiC, GaN, diamond or graphene, due to the different lattice constants, thermal expansion coefficients and thermal conductivity of different materials, can be selected according to the cost and the quality requirements of the epitaxial wafer;
[0044] (2) A buffer layer made of AlN or AlGaN superlattice structure;
[0045] (3) An unintentionally doped i-GaN drift layer of 0.5-10 μm;
[0046] (4) The P-GaN buried layer located in the i-GaN drift layer is used to deplete the electrons in the 2-DEG channel below the gate under zero bias gate voltage to achieve enhanced operation;
[0047] (5) An AlGaN barrier layer with an Al composition of 0.1 to 0.35 above the i-GaN channel layer to form a conductive 2-DEG in the i-GaN channel layer;
[0048] (6) The gate passivation layer is u...
Embodiment 2
[0052] Step ①: wafer growth. Using semiconductor material growth technologies such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE) to sequentially grow AlN or AlGaN superlattice structure buffer layers on Si, sapphire or GaN substrates, 0.5-10μm unintentional Doped i-GaN layers, such as image 3 shown;
[0053] Step ②: hard mask growth. Deposition of SiO by plasma-enhanced chemical vapor deposition (PECVD) or electron beam evaporation 2 、Si 3 N 4 Or Ni metal as a hard mask layer, and use semiconductor photolithography technology to achieve a mask opening of 1-3 μm, such as Figure 4 shown. Among them, the semiconductor photolithography technology includes a complete set of steps such as uniform coating, soft baking, exposure, development, and film hardening;
[0054] Step ③: Etching the groove of the buried layer. Use semiconductor etching technology to make the groove required for growing the buried layer, and etch the groove with a...
Embodiment 3
[0059] Step ①: wafer growth. Similar to step 1 of embodiment 2;
[0060] Step ②: hard mask growth. Similar to step 2 of embodiment 2;
[0061] Step ③: ion implantation. Use ion implantation technology to implant Mg or Fe or Mg / Al composite impurities on the surface of the sample, then remove the hard mask with buffered hydrofluoric acid BOE solution to obtain a flat GaN surface, and use thermal annealing technology to activate impurities to complete P-GaN Buried layer fabrication, such as Figure 9 shown;
[0062] Step ④: Heterojunction and passivation layer growth. Similar to step 5 of embodiment 2;
[0063] Step ⑤: fabrication of source, drain and gate electrodes. Similar to step 6 of embodiment 2.
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