Fabrication method of gate structure

Abstract

The invention discloses a method for making a gate structure. The method comprises the following steps: step one, forming a high-dielectric-constant gate dielectric layer, a polycrystalline silicon layer and a first silicon nitride layer successively; step two, carrying out photoetching to form a gate structure; step three, forming a protective layer for preventing the outside from being contaminated by the high-dielectric-constant layer; step four, forming a silicon oxide sidewall and a silicon nitride sidewall; step five, etching the silicon nitride sidewall to enable the silicon nitride sidewall to be lower than or equal to the top surface of a polysilicon gate; step six, removing the exposed silicon oxide sidewall by using a wet etching process; step seven, etching the exposed protective layer by using a comprehensive dry etching process to enable the protective layer to be lower than or equal to the top surface of the polysilicon gate; and step eight, carrying out silicon nitridewet etching processing to remove the first silicon nitride layer. Therefore, a phenomenon that a protruding barrier structure is formed at the top of the gate structure by the high-dielectric-constantprotective layer at the side of the gate structure is prevented, so that stripping of the protruding protective layer is prevented.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor integrated circuit, in particular to a manufacturing method of a gate structure. Background technique [0002] With the rise of the Internet of Things technology and the development of portable wearable devices, people's demand for low-power products is gradually increasing, which requires the development of a large number of low-power chips. Reducing the operating voltage of the chip can effectively reduce power consumption. The top silicon of the Fully Depleted-Silicon-On-Insulator (FDSOI) device will be completely depleted, so that a fully depleted channel region will be obtained, which has better isolation Characteristics and short channel effect, lower junction leakage, better random dopant fluctuation (RDF) characteristics, uniform performance of the device has been greatly improved and flexible back gate operation can be achieved, the work of the device The voltage can be reduce...

AI Technical Summary

Problems solved by technology

[0017] After the first silicon nitride layer 104 is removed, the top surfaces of the protection layer 105 and the silicon oxide sidewall 106 will be higher than the top surface of the polysilicon gate 103 and form a fence structure as shown by the dotted circle 109, protruding The fence structure is prone to peeling and forming peeling defects, which will finally affect the yield of the product

Images