Post-distortion CMOS low-noise amplifier

Abstract

The invention belongs to the field of integrated circuits, and particularly provides a post-distortion CMOS low-noise amplifier. The amplifier includes: an input stage (ML1 and MR1), a cascade stage (ML2 and MR2), a post-distortion cancellation stage (M1aL and M1aR) and resonant loads. Radio frequency differential signals are respectively input from the input stage, amplified differential output signals are respectively output from the cascade stage, and the distortion cancellation stage is NMOS transistors working in a strong inversion region, and is connected at the cascade stage. The post-distortion CMOS low-noise amplifier of the invention can significantly improve linearity of LNA, and obtain higher gain and lower noise performance at the same time.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and in particular relates to a low-noise amplifier design technology, and specifically provides a post-distortion CMOS low-noise amplifier. Background technique [0002] The scaling down of the complementary metal-oxide-semiconductor (CMOS) process allows us to easily design low-noise, low-power amplifiers. However, the linearity of CMOS transistors deteriorates due to the degradation of supply voltage and mobility. This challenge has given rise to several linearization techniques. [0003] Back in the day, the most effective linearization method was Multi-Gate Transistor (MGTR) technology, as described in T.W.Kim, B.-K.Kim, and K.-R.Lee, “Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors,"IEEE J.Solid-State Circuits,vol.39,no.1,pp.223–229,Jan.2004",such as figure 1 As shown, this technology offsets the negative third-order nonlinear...

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Problems solved by technology

[0002] The scaling down of the complementary metal-oxide-semiconductor (CMOS) process allows us to easily design low-noise, low-power amplifiers. However, the linearity of CMOS transistors deteriorates due to the degradation of supply voltage and mobility. This challenge has led to several linearization techniques

[0003] Back in the day, the most effective linearization method was Multi-Gate Transistor (MGTR) technology, as described in T.W.Kim, B.-K.Kim, and K.-R.Lee, “Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors,"IEEE J.Solid-State Circuits,vol.39,no.1,pp.223–229,Jan.2004",such as figure 1 As shown, this technology offsets the negative third-order nonlinear coefficient of the main transistor by paralleling an auxiliary transistor that works in the weak inversion region and has a positive third-order nonlinear coefficient next to the main transistor. increases the linearity of the circuit over the set voltage range; nevertheless, at high frequencies, the interaction of the second-order nonlinear coefficients and the input network generally limits the practical effectiveness of the technique

Therefore, an improved derivative superposition method was proposed to alleviate the contradiction, but it was accompanied by the complexity of the input matching network structure, and the linearity fluctuated with the matching.

On the other hand, the noise elimination technology can also obtain the improvement effect of linearity, such as the literature "Chen, Jun; Guo, Benqing;, A Highly Linear Wideband CMOS LNTA Employing Noise / Distortion Cancellation and Gain Compensation, Circuits, Systems, and Signal Processing, VOL.36, NO.2, 2017" discloses a noise-cancelling low-noise amplifier, such as figure 2 As shown, the nonlinearity of the input tube is self-eliminated by a principle similar to noise cancellation; and the nonlinearity of the auxiliary path transistor partially cancels the nonlinearity of the current mirror transistor, thereby obtaining a high linearity of 18dBm IIP3 as a whole; however, the The power consumption of the circuit is large, 27mW, and the circuit is a stack structure of 4 transistors, which makes it difficult for the circuit to work under low power supply voltage, and is not suitable for the needs of integrated circuits to scale down the power supply voltage.

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