Active area designs for charge-balanced jbs diodes

Abstract

A charge-balanced (CB) diode may include one or more CB layers. Each CB layer may include an epitaxial layer having a first conductivity type and a plurality of buried regions having a second conductivity type. Additionally, the CB diode may include an upper epitaxial layer having the first conductivity type that is disposed adjacent to an uppermost CB layer of the one or more CB layers. The upperepitaxial layer may also include a plurality of junction barrier (JBS) implanted regions having the second conductivity type. Further, the CB diode may include a Schottky contact disposed adjacent tothe upper epitaxial layer and the plurality of JBS implanted regions.

Description

Background technique [0001] The subject matter disclosed herein relates to diodes, and more particularly to active region design for charge balancing diodes. [0002] For semiconductor power devices, charge-balanced (also known as superjunction) designs offer several advantages. For example, charge-balanced devices exhibit reduced drift layer resistance and thus reduced conduction loss per unit area relative to conventional unipolar device designs. In silicon (Si) charge balance devices, multiple vertical pillars of a first dopant type (eg, p-type) can be implanted or diffused into Si device layers of a second dopant type (eg, n-type) to form the active region. The vertical pillars of these Si charge balance devices extend through the thickness of the Si epitaxial device layer (eg, tens of microns), which can be achieved using existing Si epitaxy, implantation and / or diffusion methods. [0003] However, in silicon carbide (SiC) dopants have a significantly lower diffusion c...

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Problems solved by technology

[0003] However, in silicon carbide (SiC) dopants have a significantly lower diffusion coefficient / implantation range than in Si

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