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Semiconductor structures and methods of forming them

A semiconductor and graphics layer technology, applied in semiconductor/solid-state device manufacturing, transistors, electrical components, etc., can solve problems such as large contact resistance, achieve the effects of reducing contact resistance, simplifying the process flow, and improving performance

Active Publication Date: 2021-09-07
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the semiconductor structure formed in the prior art has the problem of high contact resistance between the metal silicide and the source-drain doped layer

Method used

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  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them

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Experimental program
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Effect test

Embodiment Construction

[0033] There are many problems in the formation method of the semiconductor structure, for example, the contact resistance between the metal silicide and the plug is high.

[0034] Combining with a method of forming a semiconductor structure, the reasons for the poor performance of the formed semiconductor structure are analyzed:

[0035]figure 1 and figure 2 It is a structural schematic diagram of a method for forming a semiconductor structure.

[0036] Please refer to 1, a substrate 100 is provided, the substrate 100 includes a first region A and a second region B, the first region A has a first gate structure 111 on the substrate 100, the first gate structure The first region A substrate 100 on both sides of 111 has a first source-drain doped layer 121; the second region B substrate 100 has a second gate structure 112, and the two sides of the second gate structure 112 The substrate 100 in the second region B has a second source-drain doped layer 122; the substrate 100 h...

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Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: forming a first source-drain doped layer in a substrate exposed at the bottom of a first contact hole, and having first dopant ions in the first source-drain doped layer; A first metallization is formed on the surface of the first source-drain doped layer; after the first metallization is formed, a second contact hole is formed in the dielectric layer in the second region, and the bottom of the second contact hole exposes the substrate; A second source-drain doped layer is formed in the substrate exposed at the bottom of the hole, the second source-drain doped layer has second doping ions, and the conductivity type of the second doping ions is opposite to that of the first doping ions; A second metallization is formed on the surface of the second source-drain doping layer, and the material of the second metallization is different from that of the first metallization. The forming method can reduce the contact resistance between the first metallization and the first source-drain doping layer, and at the same time reduce the contact resistance between the second metallization and the second source-drain doping layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous advancement of semiconductor technology, the feature size of semiconductor devices is gradually reduced. The reduction of critical dimensions means that more transistors can be arranged on the chip, and at the same time, higher requirements are placed on the semiconductor process. [0003] Since metal has good electrical conductivity, in semiconductor technology, the electrical connection between the source and drain doped layers and external circuits is usually realized through metal plugs. However, since the Fermi level difference between the metal and the source-drain doped layer is relatively large, the potential barrier between the metal plug and the source-drain doped layer is relatively high, resulting in a gap between the metal plug and the source...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L27/092
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP