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Rapid testing method for system-in-package module structure

A technology of system-level packaging and module structure, which is applied in the direction of electronic circuit testing, measuring electricity, and measuring devices, and can solve the problems of unable to fit probes, high density, and increased test time

Pending Publication Date: 2019-07-12
浙江集迈科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for vertically interconnected modules, the accuracy of the interconnection cannot be guaranteed, so after the interconnection is completed, the modules must be tested to ensure that they can enter the terminal
For modules that are bonded together by wafer-level processes, because the integration of conductive bumps is too high, the density of probes per unit area needs to be high, which may cause the probes to be unable to fit.
For modules with higher integration density produced by chip to chip process, not only the above problems will exist, but also a single measurement will increase the test time

Method used

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Examples

Experimental program
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Embodiment 1

[0034] Such as Figure 1 to Figure 8 As shown, a rapid testing method for a system-in-package module structure, the specific processing includes the following steps:

[0035] 101) Processing steps of the test board 101: making TSV holes 102 on the upper surface of the test board 101 through photolithography and etching processes. The diameter of the TSV holes 102 ranges from 1um to 1000um, and the depth ranges from 10um to 1000um. An insulating layer is formed on the upper surface of the test board 101 by depositing silicon oxide or silicon nitride or direct thermal oxidation, and the thickness of the insulating layer ranges from 10 nm to 100 um. The seed layer is made on the insulating layer by physical sputtering, magnetron sputtering or evaporation process. The thickness of the seed layer ranges from 1nm to 100um. The seed layer structure adopts one or more layers. The metal material of the seed layer is titanium, copper, One or more of aluminum, silver, palladium, gold, t...

Embodiment 2

[0045] Such as Figure 7 to Figure 13 As shown, a rapid testing method for the system-in-package module structure, the specific processing includes the following steps:

[0046] 101) Processing steps of the test board 101: making TSV holes 102 on the upper surface of the test board 101 through photolithography and etching processes, the diameter of the TSV holes 102 ranges from 1um to 1000um, and the depth ranges from 10um to 1000um. An insulating layer is formed on the upper surface of the test board 101 by depositing silicon oxide or silicon nitride or direct thermal oxidation, and the thickness of the insulating layer ranges from 10nm to 100um. The seed layer is made on the insulating layer by physical sputtering, magnetron sputtering or evaporation process. The thickness of the seed layer ranges from 1nm to 100um. The seed layer structure adopts one or more layers. The metal material of the seed layer is titanium, copper, One or more of aluminum, silver, palladium, gold, ...

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Abstract

The invention discloses a rapid testing method for a system-in-package module structure. The method comprises the following steps of 101) a test board treatment step, 102) a test board retreatment step and 103) a testing step. The invention provides the rapid testing method for the system-in-package module structure for high-density integration modules in unit area.

Description

technical field [0001] The invention relates to the technical field of semiconductors, more specifically, it relates to a rapid testing method for a system-in-package module structure. Background technique [0002] The rapid development of electronic products is the main driving force for the evolution of packaging technology today. Miniaturization, high density, high frequency and high speed, high performance, high reliability and low cost are the mainstream development directions of advanced packaging. System-in-Package is one of the most important and potential technologies to meet this kind of high-density system integration. In various system-in-packages, the silicon interposer for the hermetic RF chip packaging structure is the core component of the silicon-based three-dimensional integrated RF microsystem, providing the shortest connection distance and the smallest pad for chip-to-chip and chip-to-substrate Dimensions and center spacing. Advantages of silicon interp...

Claims

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Application Information

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IPC IPC(8): G01R31/28G01R31/00
CPCG01R31/2896G01R31/00
Inventor 郑赞赞冯光建马飞陈雪平刘长春丁祥祥王永河郁发新
Owner 浙江集迈科微电子有限公司
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