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Method for manufacturing silicon cavity structure with TSV structure at bottom

A manufacturing method and cavity technology, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of high cost, unfavorable chip grounding interconnection, and bottom inequality, and achieve simple manufacturing process, cost saving and manufacturing time. Effect

Active Publication Date: 2019-07-12
浙江集迈科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For the structure where the RF chip is to be embedded in the silicon cavity, if the TSV is made first, the cavity needs to be made on the back of the adapter board, the bottom of the TSV is the bottom of the cavity, and then the interconnection is made. The depth of the TSV will vary. Do this The bottom of the bottom will be uneven, which is not conducive to the ground interconnection of the chip; if the cavity is made first, and then the TSV is made, the TSV etching process needs to be performed on the bottom of the cavity, and the cost is high

Method used

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  • Method for manufacturing silicon cavity structure with TSV structure at bottom
  • Method for manufacturing silicon cavity structure with TSV structure at bottom
  • Method for manufacturing silicon cavity structure with TSV structure at bottom

Examples

Experimental program
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Effect test

Embodiment 1

[0035] A method for manufacturing a silicon cavity 105 structure with a TSV structure at the bottom, the specific processing includes the following steps:

[0036] 101) The step of making metal pillars 103: making TSV holes 102 on the surface of the carrier 101, the depth of the TSV holes 102 is smaller than the thickness of the carrier, and filling the TSV holes 102 with metal. Such as figure 1 As shown, TSV holes 102 are formed on the upper surface of the carrier 101 by photolithography and etching processes. The TSV holes 102 have a diameter ranging from 1um to 1000um and a depth ranging from 10um to 1000um.

[0037] Such as figure 2 As shown, an insulating layer 104 such as silicon oxide or silicon nitride is deposited on the silicon wafer, or directly thermally oxidized, and the thickness of the insulating layer 104 ranges from 10 nm to 100 um. A seed layer is formed on the insulating layer 104 by physical sputtering, magnetron sputtering or evaporation process. The th...

Embodiment 2

[0046] It is basically the same as Embodiment 1, except that step 102) uses a dry etching process to make the area of ​​the TSV hole 102 on the upper surface of the carrier 101, and after performing dry etching to form the cavity 105, because the insulating layer will be damaged 104 , the insulating layer 104 may be formed again on the carrier 101 . The generation method is the same as the first time, and the thickness range of the insulating layer 104 this time is still between 10nm and 100um.

Embodiment 3

[0048] It is basically the same as Embodiment 1, the difference lies in step 102). Such as Figure 6 to Figure 8 As shown, in embodiment three, the dry etching process is used to thin the lower surface of the carrier plate 101, and the thickness of the thinning is from 100nm to 700um. The bonding process protects the surface of the carrier plate 101 on which the TSV holes 102 are provided, and then uses the temporary bonding process to protect the carrier sheet as a support to thin the lower surface of the carrier plate 101 .

[0049] In the area corresponding to the TSV hole 102, dry etching or wet etching is performed to form a cavity 105, the width of the cavity 105 is larger than the area of ​​the TSV hole 102, and the copper pillar is exposed. An insulating layer 104 is formed on the lower surface of the carrier 101 by deposition or direct thermal oxidation, and the insulating layer 104 on the surface of the copper pillars is removed by wet etching or dry etching.

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Abstract

The invention discloses a method for manufacturing a silicon cavity structure with a TSV structure at the bottom. The specific processing comprises the following steps of (101) metal pillar fabrication, (102) cavity fabrication, and (103) cavity processing. The method for manufacturing the silicon cavity structure with the TSV structure at the bottom has the advantages that the bonding and grounding of a subsequent chip are facilitated, the manufacturing process of the process is simple, and the cost and production time can be greatly saved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a silicon cavity structure with a TSV structure at the bottom. Background technique [0002] Millimeter wave radio frequency technology is developing rapidly in the semiconductor industry. It is widely used in high-speed data communication, automotive radar, airborne missile tracking system, and space spectrum detection and imaging. It is expected that the market will reach 1.1 billion US dollars in 2018 and become an emerging industry. New applications put forward new requirements for the electrical performance, compact structure and system reliability of the product. For the wireless transmitting and receiving system, it cannot be integrated into the same chip (SOC) at present, so it is necessary to integrate different chips including the radio frequency unit , filters, power amplifiers, etc. are integrated into an independent system to realize...

Claims

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Application Information

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IPC IPC(8): H01L21/768
CPCH01L21/7684H01L21/76885
Inventor 冯光建王志宇张兵周琪张勋郁发新
Owner 浙江集迈科微电子有限公司
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