Back contact solar cell with various tunnel junction structures and preparation method thereof
A technology of solar cells and tunnel junctions, applied in the field of solar cells, can solve the problems of efficiency loss, contact deterioration, metal area recombination surge, etc., to achieve high conversion efficiency, reduce process steps, and reduce the number of masks.
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[0063] A method for preparing a back-contact solar cell with multiple tunnel junction structures provided by the present invention comprises the following steps:
[0064] (1) A tunnel oxide layer is grown on the back surface of the N-type crystalline silicon substrate, and an intrinsic polysilicon layer is deposited on the tunnel oxide layer to form c-Si / SiO X / i-poly tunnel junction; deposit an oxide layer on the intrinsic polysilicon layer, and deposit an intrinsic polysilicon layer on the oxide layer to form an i-poly / Oxide / i-poly tunnel junction;
[0065] (2) Deposit a mask on the n+ doped region of the front surface; then perform phosphorus doping on the intrinsic polysilicon layer, and activate or advance phosphorus atoms at high temperature, so that the intrinsic polysilicon layer is transformed into phosphorus-doped Polysilicon layer, forming c-Si / SiO X / n+poly tunnel junction and n+poly / Oxide / n+poly tunnel junction, while forming a phosphorus-containing silicon oxide...
Embodiment 1
[0110] (1) Clean the front surface and the back surface of the N-type crystalline silicon substrate 1 respectively, remove the damaged layer and make texture, such as figure 1 Shown; Among them, the resistivity of the N-type silicon substrate is 0.3-10Ω·cm, and the thickness is 90-300μm.
[0111] (2) Perform double-sided phosphorus diffusion on the N-type crystalline silicon substrate 1 after texturing to form a double-sided n+ doped region 2, such as figure 2 As shown; the phosphorus source is phosphorus oxychloride, the diffusion temperature is 800-1000°C, and the sheet resistance of the n+ doped region after phosphorus diffusion is 150-400Ω / sq.
[0112] (3) etch the back surface of the N-type crystalline silicon substrate 1 and polish it, such as image 3 As shown; using heated TMAH or NaOH solution, the back n+ doped region 2 is removed and polished, and the weight loss of the silicon wafer is 0.1-0.5g.
[0113](4) grow an ultra-thin tunneling silicon dioxide layer 3 wi...
Embodiment 2
[0124] (1) Clean the front surface and the back surface of the N-type crystalline silicon substrate 1 respectively, remove the damaged layer and make texture, such as figure 1 Shown; Among them, the resistivity of the N-type silicon substrate is 0.3-10Ω·cm, and the thickness is 90-300μm.
[0125] (2) Perform double-sided phosphorus diffusion on the N-type crystalline silicon substrate 1 after texturing to form a double-sided n+ doped region 2, such as figure 2 As shown; the phosphorus source is phosphorus oxychloride, the diffusion temperature is 800-1000°C, and the sheet resistance of the n+ doped region after phosphorus diffusion is 150-400Ω / sq.
[0126] (3) etch the back surface of the N-type crystalline silicon substrate 1 and polish it, such as image 3 As shown; using heated TMAH or NaOH solution, the back n+ doped region 2 is removed and polished, and the weight loss of the silicon wafer is 0.1-0.5g.
[0127] (4) grow an ultra-thin tunneling silicon dioxide layer 3 w...
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