Semiconductor device with shallow trench isolation structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and provides a semiconductor device with a shallow trench isolation structure. The semiconductor device comprises a substrate, a bufferlayer and an insulating dielectric layer, at least one groove is formed in the substrate, the buffer layer is arranged on the groove wall of the groove, and the insulating dielectric layer is arrangedon the surface of the buffer layer and fills the groove. According to the semiconductor device with the shallow trench isolation structure, hot carriers are difficult to jump to the insulating dielectric layer, so that a conductive channel is not formed, and the leakage current of the semiconductor device can be improved; the buffer layer is arranged between the substrate and the insulating dielectric layer, so that the stress between the substrate and the insulating dielectric layer can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device with a shallow trench isolation structure and a method for preparing the semiconductor device with the shallow trench isolation structure. Background technique [0002] The shallow trench isolation (Shallow Trench Isolation, referred to as STI) process is a commonly used semiconductor device isolation process. Through the shallow trench isolation process, multiple memory cells can be isolated and formed, and the multiple memory cells can work independently without being affected. The effect of voltage or current changes in adjacent memory cells. [0003] Due to the shrinking size of the current Dynamic Random Access Memory (DRAM), the width of the shallow trench isolation layer becomes smaller, and the hot carriers jumping into the shallow trench isolation layer can easily form a conductive channel. As a result, a leakage current is generated, which...

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Problems solved by technology

[0003] Due to the shrinking size of the current Dynamic Random Access Memory (DRAM), the width of the shallow trench isolation layer becomes smaller, and the hot carriers jumping into the shallow trench isolation layer can easily form a conductive channel. As a result, leakage current is generated, which affects the electrical performance and product yield of semiconductor devices

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