Short-channel silicon carbide MOSFET device integrating Schottky diode and manufacturing method of short-channel silicon carbide MOSFET device

Abstract

The invention relates to a short-channel silicon carbide MOSFET device integrating a Schottky diode and a manufacturing method of the short-channel silicon carbide MOSFET device. The device comprisesa silicon carbide substrate, a silicon carbide epitaxial layer positioned on the silicon carbide substrate, a gate dielectric layer positioned on the silicon carbide epitaxial layer, and an interlayerdielectric layer positioned on the gate dielectric layer; metal is deposited on the back of the silicon carbide substrate to form drain contact; a P-well B region 2 and a P-well A region are arrangedbetween the silicon carbide epitaxial layer and the gate dielectric layer from bottom to top; a P-type impurity ion region and an N-type impurity ion region are arranged in the P-well A region; a gate is arranged on the gate dielectric layer; and a metal layer is deposited on the interlayer dielectric layer to form a source. According to the manufacturing method of the device, P wells B are usedfor manufacturing a side wall, so that an N+ source region is self-aligned with the P wells B, and therefore, a channel length L is realized; the P wells of the source region are separated, an N-epitaxy is enabled to contact with the source end metal; and because the concentration of the N-epitaxy is relatively low, the N-epitaxy and the source end metal form Schottky contact, so that the Schottkydiode is integrated into the short-channel silicon carbide MOSFET.

Description

technical field [0001] The invention relates to the technical field of silicon carbide MOSFET devices, in particular to a short-channel silicon carbide MOSFET device integrated with Schottky diodes through a self-aligned manufacturing method. Background technique [0002] Since the diffusion coefficients of N-type and P-type impurities in silicon carbide are extremely small, it is impossible to achieve channel self-alignment through lateral diffusion of N-well or P-well like silicon-based MOSFETs. At present, silicon carbide MOSFET devices of the traditional method are mainly manufactured by non-self-alignment process. The main process of the process is as follows: ① Deposit an oxide layer on the N-type silicon carbide epitaxy (subsequently called hardmask), P+ photolithography, and etching Oxide layer, glue removal, and then implant P-type impurities to form P+ contact, remove hardmask; ② Deposit oxide layer, P well photolithography, etch oxide layer, remove glue, then inje...

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Problems solved by technology

[0003] like figure 1 As shown, the traditional manufacturing method forms the channel length L by photolithography of the P well and the N+ source region. Since the overlay error ΔL inevitably exists between the two layers of lithography, in order to avoid the influence of the overlay error ΔL on the device performance, the When designing the device, it is necessary to take the overlay error ΔL into consideration, and the designed channel length should be L+ΔL, so that the designed silicon carbide MOSFET device has a longer channel length, and the formula Ron=L / [k* W*(VGS-Vth)], it can be seen that due to the increase of L, the on-resistance Ron of MOSFET will inevitably increase; and because the process error is random, it will lead to random discrete distribution of device performance, affecting Device Parameter Consistency

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