Insulating layer buried transistor structure and device

Abstract

The invention discloses an insulating layer buried transistor structure and a device. The insulating layer buried transistor structure comprises a semiconductor substrate, a source electrode, a grid electrode, and a drain electrode, wherein a channel layer, an isolation layer, and a barrier layer are sequentially grown on a supporting substrate; the grid electrode is arranged between the source electrode and the drain electrode; an insulating layer is arranged between the supporting substrate and the channel layer; and the supporting substrate is a substrate compatible with an insulating layergrowth process. The transistor comprises a back gate control electrode and an isolation layer, wherein the back gate control electrode is isolated from the channel layer through an isolation layer. The beneficial effects are that the leakage of the substrate is effectively blocked, the leakage current among the grid electrode, the source electrode and the supporting substrate is improved / controlled, and the noise coefficient is reduced; crystal chapping deformation and reliability reduction caused by growth of lattice mismatch materials are avoided; and the threshold voltage can be controlledthrough the back gate control electrode, and the leakage current is further reduced, so that various novel functional devices are developed.

Description

technical field [0001] The invention relates to the field of transistors, in particular to an insulating layer buried type transistor structure and device. Background technique [0002] The existing III-V compound semiconductors include GaAs, GaN, InP and other types. In the GaAs pHEMT substrate structure, the undoped InGaAs layer and the AlGaAs layer form a heterojunction at the interface to generate a two-dimensional electron gas. The gate controls the barrier height, and when the gate reaches a certain bias voltage, the two-dimensional electron gas tunnels across the barrier to form a current between the source and drain. In order to prevent the current from leaking into the GaAs substrate, an undoped GaAs / AlGaAs superlattice buffer layer is added. However, the existing GaAspHEMT transistors have the following disadvantages: large leakage current, including the leakage current between the gate and the source, and the two-dimensional electron gas leaks to the GaAs substr...

AI Technical Summary

Problems solved by technology

However, the existing GaAspHEMT transistors have the following disadvantages: large leakage current, including the leakage current between the gate and the source, and the two-dimensional electron gas leaks to the GaAs substrate through the undoped GaAs / AlGaAs superlattice buffer layer current; the efficiency of GaAs pHEMT transistors is significantly reduced due to the existence of leakage current; the stackability of GaAs pHEMT devices is not good due to the existence of leakage current

GaN (GaN-on-SiC) on silicon carbide (SiC) substrates developed on this basis, and GaN (GaN-on-Si) on Si (silicon) substrates, the main advantage of SiC substrates is the heat dissipation characteristics , GaN (GaN-on-SiC) on silicon carbide (SiC) substrates is mainly suitable for high-frequency, high-voltage, high-temperature applications, and its main disadvantages are: the size of the substrate is limited, the cost is relatively high, and it is difficult to integrate with CMOS, etc. Si-based technology integration

However, GaN (GaN-on-Si) on Si (silicon) substrates also has some problems, which are manifested in: poor high-frequency characteristics, poor reliability, large leakage current and low efficiency

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