Patterned hard mask layer preparation method, capacitor array structure and preparation method thereof

Abstract

The invention provides a method for preparing a patterned hard mask layer, a capacitor array structure and a method for preparing the same. A hard mask layer is provided, and a first organic material layer and a second organic material layer are sequentially deposited thereon, and the second organic material layer is partially etched along the first direction and the second direction; and then the hard mask layer is deposited layer on the sidewall of the etched second organic material layer, use the etched second organic material layer and the hard mask thin layer as a mask to etch the first organic material layer until the hard mask layer is exposed, and A pattern of windows arranged in a honeycomb arrangement is formed on the first organic material layer. The technical solution of the invention significantly increases the density of capacitor holes, so more capacitors can be provided under the same size. For the same number of capacitors, the size of the chip in the present invention is smaller, which is beneficial to realize the reduction of device size.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for preparing a patterned hard mask layer, a capacitor array structure and a method for preparing the same. Background technique [0002] As one of the necessary components in integrated circuits, capacitors have functions such as voltage adjustment and filtering in circuits, and are widely used in integrated circuits. In the Dynamic Random Access Memory (DRAM for short) process below 20nm, the DRAM adopts a stacked capacitor structure, and its capacitor (Capacitor) is in the shape of a vertical cylinder with a high aspect ratio. Vertical capacitors form deep grooves in the substrate, and use the sidewalls of the deep grooves to provide the main plate area, thereby reducing the area occupied by the capacitor on the chip surface, while still obtaining a large capacitance. [0003] However, as the chip size continues to decrease, the...

AI Technical Summary

Problems solved by technology

[0004] In the prior art, the multi-pass photolithography process prepares and forms the capacitance hole of the capacitor, so that there is a problem of misalignment of the photomask in the photolithography process, which will affect the electrical connection and isolation between the components in the memory. The performance of the subsequently formed memory, and also detrimental to achieving component size reduction

Images