Power semiconductor device and manufacturing method thereof

Abstract

According to the manufacturing method of the power semiconductor device provided by the invention, the side wall is formed on the side wall of the shielding gate polycrystalline silicon layer, and theside wall is positioned above the trench on the outer side of the shield gate polycrystalline silicon layer, so the connecting holes can be directly formed in the shielding gate polycrystalline silicon layer, a mask plate for defining the area where the connecting holes are connected with the gate is omitted, procedures are reduced, the process cost is reduced, and contact between the connectingholes formed in the shielding gate polycrystalline silicon layer subsequently and the gate polycrystalline silicon layer is avoided. The side wall protects the second oxide layer, the subsequent formation of the source electrode is avoided, ions are implanted into the second oxide layer during N-type ion implantation at the upper part, the performance of the second oxide layer is prevented from being reduced, and N-type ions are prevented from scattering downwards through the thinned part of the second oxide layer to enter a P-type ion implantation region during N-type ion implantation, so that the influence of the N-type ions on a channel is avoided, the threshold voltage of the device is improved, and the electrical property of the power semiconductor device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a power semiconductor device and a manufacturing method thereof. Background technique [0002] As the integration level of semiconductor devices becomes higher and higher, the pitch of integrated circuits becomes smaller and smaller. The shielded gate polysilicon layer (sourcepoly) of the shielded gate trench (SGT, Split gate trench) in the power semiconductor device cannot be directly drawn out, that is, the connection hole (contact) cannot be directly provided on the shielded gate polysilicon layer, because the connection hole The alignment and CD value have very high requirements, so a special mask is required to define the preset area A (such as Figure 1a As shown), this makes the degree of integration of the semiconductor device lower, and a special photomask is required to form the preset area, which makes the process cost higher. In addition,...

AI Technical Summary

Problems solved by technology

The shielded gate polysilicon layer (sourcepoly) of the shielded gate trench (SGT, Split gate trench) in the power semiconductor device cannot be directly drawn out, that is, the connection hole (contact) cannot be directly provided on the shielded gate polysilicon layer, because the connection hole The alignment and CD value have very high requirements, so a special mask is required to define the preset area A (such as Figure 1a As shown), this makes the integration of semiconductor devices lower, and a special photomask is required to form the preset area, making the process cost higher

In addition, when the gate polysilicon layer is formed, the problem of inconsistency of the gate polysilicon layer is prone to occur, resulting in poor electrical performance of the formed power semiconductor device

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