Nanowire ion grid control synaptic transistor and preparation method thereof

Abstract

The invention discloses a nanowire ion grid control synaptic transistor and a preparation method thereof, and belongs to the field of synaptic devices oriented to neural network hardware application.According to the invention, the advantages of good one-dimensional transport characteristic of fence nanowires and low operating voltage in an ion grid control double-electric-layer system are combined, and compared with the existing planar large-size synaptic transistor based on a two-dimensional material or an organic material, the nanowire ion grid control synaptic transistor of the invention can achieve low power consumption and small area overhead; and due to the excellent device consistency and CMOS rear-end integration characteristic, the nanowire ion grid control synaptic transistor has the potential to be applied to a future large-scale neuromorphic calculation circuit.

Description

technical field [0001] The invention relates to the field of synaptic devices oriented to the application of neural network hardware, in particular to an ion-gated synaptic transistor with the advantages of low power consumption, high consistency and good CMOS process compatibility and a preparation method thereof. Background technique [0002] The era of big data puts forward new requirements for computing power and energy efficiency of computers. Computers based on the traditional von Neumann architecture have problems such as separation of storage and calculation and low intelligence caused by restrictions on preset programs. The neuromorphic computing of non-Feng architecture has attracted more and more attention because of its advantages of high energy efficiency, high parallelism and high fault tolerance in processing tasks such as recognition, classification and decision-making. Neuromorphic computing needs to be developed one by one from the level of device, circuit ...

AI Technical Summary

Problems solved by technology

Among them, ion-gated synaptic transistors have the advantages of good biomimeticity, flexible devices, and read-write separation, but there are challenges such as difficult integration, large area overhead, and high power consumption.

[0004] Specifically, the problem of difficulty in integration is mainly reflected in the fact that the current ion-gated synaptic transistors mainly use liquid gates or colloidal gates, which are not easy to integrate. In addition, synaptic transistor arrays based on such immature materials and processes have devices Therefore, it is necessary to seek excellent solid-state electrolytes and good integration solutions

[0005] In addition, the channel materials of the current synaptic transistors generally use two-dimensional and organic materials, which are poorly compatible with CMOS processes, and the area of ​​the synaptic devices prepared by them is large and consumes high power.

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