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Systems and methods for ecc architecture with memory mapping

A technology of memory mapping and memory, applied in the field of error correction code architecture, to improve system performance, increase ECC throughput, and reduce power consumption

Pending Publication Date: 2020-09-22
INNOGRIT TECH CO LTD
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  • Claims
  • Application Information

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Problems solved by technology

Additionally, in multi-channel storage or communication systems, conventional ECC architectures require separate channel buffers to service each channel

Method used

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  • Systems and methods for ecc architecture with memory mapping
  • Systems and methods for ecc architecture with memory mapping
  • Systems and methods for ecc architecture with memory mapping

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Embodiment Construction

[0012] Specific embodiments according to the present application will now be described in detail with reference to the accompanying drawings. For consistency, the same elements in the various figures are denoted by the same reference numerals.

[0013] The present specification provides devices, systems and methods supporting various high-speed non-volatile memories (NVMs) and any combination of various NVMs. As used herein, a non-volatile memory device can be a computer memory device that can retain stored information after power has been removed and that can be retrieved after power is cycled (turned off and back on). Non-volatile memory devices can include floppy disks, hard drives, magnetic tape, optical disks, NAND flash memory, NOR flash memory, magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM) ), Nano random access memory (Nano-RAM), and so on. In the description, NAND flash memory may be use...

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Abstract

Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may comprise an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory comprising a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation statusof the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Description

technical field [0001] This specification relates to an error correcting code (ECC) architecture, and more particularly to an ECC architecture with a flexible memory map. Background technique [0002] ECC has been widely used in data storage and communication systems to recover user data by a receiver or reader even when many errors (not exceeding the capability of the code used) are introduced due to data corruption during transmission or in memory . Conventional ECC architectures usually have an encoder path and a decoder path, which require separate encoding buffers and decoding buffers during encoding and decoding. Furthermore, in multi-channel storage or communication systems, conventional ECC architectures also require separate channel buffers to service each channel. Therefore, there is a need in the art for an ECC architecture that can organize and utilize resources to achieve faster throughput and lower power consumption. Contents of the invention [0003] The ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10G06F12/0873
CPCG06F11/10G06F12/0873G06F11/1048G06F11/3055G06F11/3034G06F11/3409G06F12/0246G06F2212/7201G06F2212/7208G06F2212/1028G06F2212/1032G06F2212/7203Y02D10/00G06F11/1068
Inventor 不公告发明人
Owner INNOGRIT TECH CO LTD
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