Novel InAs-GaSb TFET suitable for planar process

Abstract

The invention relates to a novel InAs-GaSb TFET suitable for a planar process. The novel InAs-GaSb TFET comprises a substrate; a source region arranged on the substrate; a first drain region arrangedon the substrate and positioned in the source region; a channel layer arranged on the source region; a second drain region arranged on the first drain region; a gate dielectric layer arranged on the channel layer and the second drain region; a gate electrode arranged on the gate dielectric layer; a source electrode arranged on the source region; and a drain electrode arranged on the second drain region. According to the novel InAs-GaSb TFET of the invention, a first drain region and a second drain region are arranged, the first drain region is located in the source region, a heavily doped drain region pn junction is introduced through an optimization process of first epitaxy and second injection, effective electrical isolation between the source region and the drain region is electricallyrealized by utilizing the electrical isolation characteristic of the reverse biased pn junction, and the preparation process is simple and highly compatible with the traditional planar CMOS process.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to a novel InAs-GaSb TFET suitable for planar technology. Background technique [0002] CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor), as the most basic unit of VLSI, has always attracted the attention of academia and industry. In order to continuously improve the performance of integrated circuits, the size of CMOS devices has been shrinking, so that more transistors can be accommodated in an integrated circuit chip of the same size. With the continuous reduction of the size of CMOS devices, the density of transistors in the chip is getting larger and larger, but at the same time as the performance of ultra-high-density integrated circuits is improved, the power consumption density of the chip will also rise sharply. Will seriously affect the reliability of integrated circuits. Moreover, as the feature size of MOSFET ...

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Problems solved by technology

[0004] At present, most of the researches on InAs / GaSb TFETs are vertical structures. In addition, in order to achieve effective source-drain isolation, it is necessary to form an "air bridge" structure or a "cantilever" structure by wet etching. The preparation process of this structure It is extremely complex and difficult to be compatible with the traditional planar process, and the suspended channel is easy to break, which will cause serious reliability problems

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