Shield gate field effect transistor and forming method thereof

Abstract

The invention provides a shield gate field effect transistor and a forming method thereof. A gate oxide layer is prepared by combining the thermal oxidation process and the deposition process, the overall thickness of the gate oxide layer is reduced, and the thickness of the oxide layer at the corner position is increased based on the deposition oxide layer with high coverage performance, so thatthe problem of mutual restriction of device turn-on voltage and device leakage current in the prior art can be effectively solved, and the voltage withstanding performance of the device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a shielded gate field effect transistor and a forming method thereof. Background technique [0002] A shielded gate field effect transistor (Shielded Gate Trench, SGT) is more conducive to the flexible application of semiconductor integrated circuits because of its low gate-to-drain capacitance Cgd, very low on-resistance, and high withstand voltage performance. Specifically, in the shielded gate field effect transistor, by setting the shielding electrode below the gate electrode, the gate-to-drain capacitance can be greatly reduced, and the drift region of the shielded gate field effect transistor also has a relatively high impurity carrier Concentration, can provide additional benefits to the breakdown voltage of the device, which can reduce the on-resistance accordingly. [0003] In some application scenarios, a low voltage shielded gate field effect transistor is requ...

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Problems solved by technology

[0006] The purpose of the present invention is to provide a method for forming a shielded gate field effect transistor to solve the problem of mutual restriction between the turn-on voltage of the device and the leakage current phenomenon of the device

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