Split-gate trench MOSFET and manufacturing method thereof
A manufacturing method and groove technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of unfavorable device cost control, difficult filling process, high cost of grinding process, etc., to save CMP grinding process, The effect of enhancing market competitiveness and reducing device production costs
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[0050] Embodiment 1: The process method for improving gate leakage of split-gate trench MOSFET described in this embodiment is realized through the following steps:
[0051] Step 1: grow an N-type epitaxial layer 2 on the surface of the Si substrate 1, the thickness of the epitaxial layer is determined according to the source-drain withstand voltage required by the device, ranging from 2 microns to 20 microns, such as figure 2 shown.
[0052] Step 2: Deposit a layer of silicon oxide on the surface of the epitaxial layer, define a trench area on the surface of the silicon oxide by photolithography, and then use the silicon oxide as a hard mask to etch the silicon substrate to form a deep trench and move it In addition to the silicon oxide on the surface, the depth of the deep trench formed by dry etching in the second step is between 2 microns and 20 microns, and the width is between 0.2 microns and 3 microns, such as image 3 Show;
[0053] Step 3: grow silicon oxide 3 in t...
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