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Split-gate trench MOSFET and manufacturing method thereof

A manufacturing method and groove technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of unfavorable device cost control, difficult filling process, high cost of grinding process, etc., to save CMP grinding process, The effect of enhancing market competitiveness and reducing device production costs

Pending Publication Date: 2021-03-12
SUZHOU KAIWEITE SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The HDP filling process is difficult, and if the filling is not good, it is easy to form voids 1. The thickness of the IPO will be uneven during wet etching, causing gate-source leakage, especially for small-sized cells.
In addition, the cost of CMP grinding process is high, which is not conducive to device cost control

Method used

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  • Split-gate trench MOSFET and manufacturing method thereof
  • Split-gate trench MOSFET and manufacturing method thereof
  • Split-gate trench MOSFET and manufacturing method thereof

Examples

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Embodiment 1

[0050] Embodiment 1: The process method for improving gate leakage of split-gate trench MOSFET described in this embodiment is realized through the following steps:

[0051] Step 1: grow an N-type epitaxial layer 2 on the surface of the Si substrate 1, the thickness of the epitaxial layer is determined according to the source-drain withstand voltage required by the device, ranging from 2 microns to 20 microns, such as figure 2 shown.

[0052] Step 2: Deposit a layer of silicon oxide on the surface of the epitaxial layer, define a trench area on the surface of the silicon oxide by photolithography, and then use the silicon oxide as a hard mask to etch the silicon substrate to form a deep trench and move it In addition to the silicon oxide on the surface, the depth of the deep trench formed by dry etching in the second step is between 2 microns and 20 microns, and the width is between 0.2 microns and 3 microns, such as image 3 Show;

[0053] Step 3: grow silicon oxide 3 in t...

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Abstract

The invention relates to a process method for improving gate-source electric leakage of a split-gate trench MOSFET. An isolation oxide layer between gate-source polycrystalline silicon of the split-gate trench MOSFET is composed of boron phosphorosilicate glass (BPSG). The the gate trench is filled with the BPSG material, and then the BPSG on the surface of the silicon wafer and on the side wall of the trench flows to the bottom of the gate trench through high-temperature backflow, so that the thickness of the BPSG oxide film at the bottom of the gate trench is increased, the thickness of theBPSG oxide film on the surface of the silicon wafer and on the side wall of the trench is reduced, and the redundant BPSG oxide film on the surface of the silicon wafer and the side wall of the trenchis removed by a wet method. According to the split-gate trench MOSFET manufactured through the method, the problem of gate-source electric leakage of a device is effectively solved, meanwhile, it iseasier to fill an oxide film between polycrystalline silicon, the process difficulty is lowered, and the smaller device size can be better achieved. Meanwhile, a silicon oxide CMP process can be saved, and the production cost of the device is reduced.

Description

technical field [0001] The invention relates to a process and manufacturing method for improving gate-source leakage of split-gate trench MOSFETs, belonging to the technical field of semiconductor power devices. Background technique [0002] Split-gate trench MOSFET uses the principle of oxide layer charge coupling to break the theoretical silicon limit of traditional trench power MOSFET, so that the N-type drift region can achieve a higher breakdown voltage of the device even under the condition of high doping concentration, thus Obtain low on-resistance, and at the same time add excellent switching characteristics, gradually replacing traditional trench devices. In the split-gate trench MOSFET structure, the fabrication of the isolation oxide layer (Inter-Poly Oxide, referred to as IPO) between the gate and source polysilicon is a very important part of the split-gate trench device process, and its fabrication process has an impact on device performance and cost. Very big...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/417H01L29/423
CPCH01L29/7831H01L29/66484H01L29/41766H01L29/4236
Inventor 谭在超丁国华罗寅
Owner SUZHOU KAIWEITE SEMICON
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