Preparation method of three-dimensional broken line nanowire array vertical field effect transistor

Abstract

The invention discloses a preparation method of a three-dimensional broken line nanowire array vertical field effect transistor. The preparation method comprises the following steps: 1), etching a three-dimensional step shape on a patterned substrate by using an etching technology; 2), depositing a dielectric film layer on the substrate etched with the three-dimensional step, performing etching again to expose the heterogeneous side wall near the three-dimensional step, and constructing a guide channel on the heterogeneous side wall by using selective etching; 3), preparing nano-scale catalytic metal particles in a guide channel formed by heterogeneous side walls; 4), depositing and covering an amorphous semiconductor precursor film layer corresponding to the nanowire to be grown on the surface of the whole structure; 5), raising the temperature to convert the nanoscale catalytic metal particles into a liquid state from a solid state in the guide channel, starting to absorb the amorphous layer at the front end, and separating out the broken-line-shaped crystalline nanowire at the rear end; and 6), preparing a short-channel field effect transistor by taking the vertical part of thebroken-line-shaped crystalline nanowire as a channel region and the horizontal part as a source and drain electrode region.

Description

technical field [0001] The invention relates to a three-dimensional batch growth method of nanowires, in particular to obtain a sidewall channel by depositing a heterogeneous stack on steps for etching, and using a plane solid-liquid-solid (IPSLS) method to grow three-dimensional folded line nanowires Array method; belongs to the field of microelectronics technology. Background technique [0002] Junctionless transistors are key to developing a new generation of high-performance micro- and nanoelectronic logic, sensing, and display applications. Most of the nanowires prepared by the common gas-liquid-solid (VLS) growth mode are vertical random arrays, and it is difficult to directly achieve reliable and low-cost positioning integration in the current planar electronic process. Based on top-down electron beam writing (EBL) technology, nanowires with diameters of 10 to 100 nanometers and channel lengths in the order of 10 to 100 nanometers have been fabricated. The excellent ...

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Problems solved by technology

The nanowires prepared by the common vapor-liquid-solid (VLS) growth mode are mostly vertical random arrays, and it is difficult to directly realize reliable and low-cost positioning integration in the current planar electronic process.

Based on the top-down electron beam direct writing (EBL) technology to prepare transistor structures with nanowire diameters of 10-100 nanometers and channel lengths on the order of ten to hundreds of nanometers, the excellent characteristics of various new nanowire functional devices have been verified. , but due to factors such as high preparation cost and low yield, it is difficult to obtain large-scale and industrial applications

Through the bottom-up planar solid-liquid-solid (IP-SLS) nanowire growth catalyzed by nano-metal droplets, crystalline silicon, germanium and various alloy semiconductors with diameters below 100 nanometers can be prepared in large quantities by photolithography Nanowires can be used to prepare planar transistor arrays, but due to the limitations of the conventional photolithography process, the minimum channel length is relatively high, and it is impossible to prepare devices with shorter channels

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