Piezoelectric film composite substrate and preparation method thereof
A piezoelectric thin film and composite substrate technology, which is applied in the manufacture/assembly of piezoelectric/electrostrictive devices, circuits, electrical components, etc., can solve problems such as increased optical transmission loss, excessive wafer warpage, and thin film shedding , to achieve the effect of reducing loss, reducing optical loss, and preventing warpage
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Embodiment 1
[0094] First, a silicon wafer substrate having a size of 3 inches and a thickness of 0.4 mm is prepared, and the silicon wafer substrate has a smooth surface. After the silicon wafer substrate is thoroughly cleaned, PECVD is used to alternately deposit Si on the upper surface and the bottom surface of the silicon wafer substrate facing away from each other. 3 N 4 layer and SiO 2 Floor.
[0095] Specifically, Si is first deposited on the upper surface of the silicon wafer substrate 3 N 4 layer, then the Si 3 N 4 SiO 2 layers, repeated alternately in sequence to form a stacked structure consisting of 5 layers of Si 3 N 4 layer / SiO 2 layer isolation layer. Similarly, Si was alternately deposited on the bottom surface of the Si wafer substrate 3 N 4 layer and SiO 2 layer to form a stacked structure consisting of 5 Si 3 N 4 layer / SiO 2 Compensation layer for layers. In the isolation layer and compensation layer, Si 3 N 4 layer and SiO 2 Each of the layers may ha...
Embodiment 2
[0098] First, a silicon wafer substrate having a size of 3 inches and a thickness of 0.4 mm is prepared, and the silicon wafer substrate has a smooth surface. After the silicon wafer substrate is thoroughly cleaned, LPCVD is used to alternately deposit Si on the upper surface and the bottom surface of the silicon wafer substrate facing away from each other. 3 N 4 layer and SiO 2 Floor.
[0099] Specifically, Si is first deposited on the upper surface of the silicon wafer substrate 3 N 4 layer, then the Si 3 N 4 SiO 2 layers, repeated alternately in sequence to form a stacked structure consisting of 6 layers of Si 3 N 4 layer / SiO 2 layer isolation layer. Similarly, Si was alternately deposited on the bottom surface of the Si wafer substrate 3 N 4 layer and SiO 2 layer to form a stacked structure consisting of 6 Si 3 N 4 layer / SiO 2 Compensation layer for layers. In the isolation layer and compensation layer, Si 3 N 4 layer and SiO 2 Each of the layers may ha...
Embodiment 3
[0103] First, a silicon wafer substrate having a size of 4 inches and a thickness of 0.4 mm is prepared, and the silicon wafer substrate has a smooth surface. After the silicon wafer substrate is thoroughly cleaned, LPCVD is used to alternately deposit Si on the upper surface and the bottom surface of the silicon wafer substrate facing away from each other. 3 N 4 layer and SiO 2 Floor.
[0104] Specifically, Si is first deposited on the upper surface of the silicon wafer substrate 3 N 4 ) layer, then the Si 3 N 4 SiO 2 layers, repeated alternately in sequence to form a stacked structure consisting of 4 layers of Si 3 N 4 layer / SiO 2 layer isolation layer. Similarly, Si was alternately deposited on the bottom surface of the Si wafer substrate 3 N 4 layer and SiO 2 layer to form a stacked structure consisting of 4 Si 3 N 4 layer / SiO 2 Compensation layer for layers. In the isolation layer and compensation layer, Si 3 N 4 layer and SiO 2 Each of the layers may ...
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Abstract
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