Circuit for parallel multiply-accumulate operation in binary neural network formed based on RRAM array

Abstract

The invention discloses a circuit for parallel multiply-accumulate operation in a binary neural network formed based on an RRAM (Resistance Random Access Memory) array, a storage array formed based on 1T1R units is a 64 * 64 RRAM array adopting a pseudo cross structure, and each 1T1R unit is formed by an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) and a resistive random access memory; the word lines WL of each row of the storage array are connected with the parallel input circuit, so that 64 data in the maximum 8 * 8 weight matrix and 64 data stored in the storage array complete binary neural network BNN convolution operation; the bit line BL of each column of the storage array is connected with the current input end of the cascade current mirror circuit, and the output end of the cascade current mirror circuit is connected to the upper pole plate of the output capacitor. According to the circuit, the problems of crosstalk among different nodes and easy damage of stored data during multi-row reading of storage units in a traditional SRAM (Static Random Access Memory) are solved, the reliability of a system is improved, and the leakage power consumption among the units is reduced.

Description

technical field [0001] The present invention relates to the technical field of integrated circuit design, in particular to a parallel multiply and accumulate (MAC) operation in a binary neural network based on a resistive random access memory (Resistive Random Access Memory, abbreviated as RRAM) array circuit. Background technique [0002] At present, various artificial intelligence devices have extremely high requirements on the size and power consumption of electronic devices. Current neural networks generally use floating-point calculations, which require large storage space and calculations, and the resulting high power consumption is serious. hinders mobile applications. [0003] In order to effectively reduce the long delay and high power consumption caused by complex multiplication and accumulation operations, the existing technology proposes a binary neural network (Binarized Neural Networks, BNN), which converts signals such as weights, inputs, and hidden layer out...

AI Technical Summary

Problems solved by technology

[0002] At present, various artificial intelligence devices have extremely high requirements on the size and power consumption of electronic devices. Current neural networks generally use floating-point calculations, which require large storage space and calculations, and the resulting high power consumption is serious. Hinders mobile applications

[0003] In order to effectively reduce the long delay and high power consumption caused by complex multiplication and accumulation operations, the existing technology proposes a binary neural network (Binarized Neural Networks, BNN), which converts signals such as weights, inputs, and hidden layer outputs into binary value, and then encode the binary code as 0 and +1 or -1 and +1, which can effectively reduce the power consumption caused by the large amount of storage resources occupied by the neural network and the frequent data access during the reasoning process, but the traditional SRAM storage unit has the difficulty of storing data. Defects, low reliability, high power consumption, etc., but there is a lack of corresponding solutions in the prior art

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