Multi-valued memory

Abstract

The embodiment of the invention discloses a multi-valued memory. The multi-valued memory comprises a plurality of memory sub-columns; each storage sub-column comprises a floating diffusion region and a plurality of storage units; the storage unit at least comprises a charge storage area and a corresponding transfer transistor; a part of a channel of the transfer transistor is in the vertical direction, and transfer of charges of the transfer transistor between the floating diffusion region and the charge storage region is controlled through polycrystalline silicon gate structures located on the two sides of the channel of the transfer transistor. According to the embodiment of the invention, the transfer transistor of which the partial channel is in the vertical direction is applied to the multi-valued memory, and the photodiode is used as a charge storage region, so that the integration density of the transfer transistor is improved, and the chip preparation cost is reduced.

Description

technical field [0001] The invention relates to the field of storage processing, in particular to a multi-value memory. Background technique [0002] The stored data of random access memory (RAM, random access memory) can be read or written on demand, and the speed of reading and writing has nothing to do with the storage location of the data. This kind of memory has the fastest read and write speed in the memory, but it will lose its stored data when the power is turned off, so it is mainly used to store data for short-term use. According to different stored information, random access memory can be divided into static random access memory (Static RAM, SRAM) and dynamic random access memory (Dynamic RAM, DRAM). [0003] An existing SRAM such as figure 1 As shown, the storage unit is a flip-flop composed of 6 MOS transistors, namely the first MOS transistor P0, the second MOS transistor P1, the third MOS transistor N0, the fourth MOS transistor N1, the fifth MOS transistor ...

AI Technical Summary

Problems solved by technology

The capacitor C1 of DRAM is generally formed in a stacked or trenched manner. The advantage is that it occupies a small area and can achieve a large capacity. The disadvantage is that the process is much more complicated than the logic circuit, and the access speed is slower than that of SRAM.

Another disadvantage of DRAM is that the memory cells are based on the amount of charge stored on capacitor C1, which decreases with time and temperature and must therefore be refreshed periodically to maintain the correct information they originally remembered

Another disadvantage of DRAM is that due to the conductive interconnection between capacitor C1 and MOS transistor M1, there is a contact hole for conductive interconnection, which needs to be in contact with the silicon surface when interconnecting with the MOS transistor. In this way, there will be an interface state at the contact interface between the contact hole and the silicon, and the electrons in the interface state are relatively active (plasma etching is required when making the contact hole, which will cause damage to the chip surface, and the contact of the two interfaces will be damaged at the same time. There are interface states. Due to the existence of interface states, there are a large number of defect centers on the surface, which makes it easy for carriers to be captured and released on the surface, which greatly increases leakage), and leakage is a problem that is very difficult to control, (increased leakage will lead to refresh Time is shortened, power consumption is increased), and DRAM and SRAM will have reset noise when reading and writing

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