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Vertical high-power field-effect transistor unit structure

A field-effect transistor and cell structure technology, applied in electrical components, semiconductor devices, semiconductor/solid-state device manufacturing, etc., can solve the problems of reducing device switching speed, large gate parasitic capacitance, and increasing circuit cost, and achieve a reduction in Effects of on-resistance, thermal impedance, small gate parasitic capacitance, and high withstand voltage

Inactive Publication Date: 2003-10-22
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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  • Abstract
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Problems solved by technology

The main disadvantages of using this structure are: 1. It is not suitable for manufacturing high-voltage short-channel MOS power devices
2. The MOSFET formed by the planar diffusion process has a polycrystalline gate parallel to the surface of the silicon wafer, and the parasitic capacitance of the gate is large, thus greatly reducing the switching speed of the device
3. Although the channel resistance can be reduced by increasing the channel width, the cost of doing so is to occupy a large amount of valuable chip area and increase the cost of the circuit

Method used

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  • Vertical high-power field-effect transistor unit structure

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Embodiment Construction

[0016] The present invention is further described below by way of examples.

[0017] 1. On an N-type (100) silicon substrate with a resistivity of 0.001 ohm-cm, epitaxy two layers of N-type thin layers by chemical vapor deposition, wherein the first epitaxial layer is adjacent to the silicon substrate and has a thickness of The thickness of the second epitaxial layer is 3.5 microns, and the resistivity is 0.3 ohm-cm. On the second epitaxial layer, a groove with a depth of 1.5-2.5 microns and a width of 1.0-1.5 microns is etched by plasma method.

[0018] 2. Thermally grow a layer of silicon dioxide on the silicon wafer with a thickness of 50 nanometers, and then deposit a layer of silicon nitride with a thickness of 150 nanometers by chemical vapor deposition. Then, a layer of photoresist masking film is formed by photolithography to expose the area where the trench is to be formed, and mask other areas with photoresist. The silicon nitride and silicon dioxide that are not m...

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Abstract

This invention relates to a vertical N channel MOS high-power field-effect transistor structure applying etching channel method on N silicon epitaxial chip to make grating oxygen layer of the fieldistor and W grating electrode in the channel of the silicon epitaxial film, W grating and silicon chip are vertical on the surface, when the fieldistor in working condition, the current flows from the drain of the silicon chip bottom through an inversion channel zone to get to the source vertical to silicon chip surface.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a vertical N-channel metal-oxide-semiconductor high-power field-effect transistor unit structure. Background technique [0002] Before the invention of metal-oxide-semiconductor high-power field-effect transistors, only high-power bipolar transistors could be used in the high-speed, medium-power range. High-power bipolar transistors were invented in the early 1950s. With the continuous improvement of technology, people can manufacture bipolar high-power transistors with an operating current of hundreds of amperes and a withstand voltage of up to 600 volts. However, there are some essential defects in the working performance of bipolar high-power transistors. First of all, the bipolar high-power transistor is a current control device, which requires a large base current to ensure its stability in a certain working state, usually 1 / 5-1 / 10 of t...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/78
Inventor 徐小诚缪炳有陈志伟汪激扬
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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