New-type RISC pieline microcontroller structure and its operation method

A microcontroller and pipeline technology, applied in microcontroller devices, program control design, instruments, etc., can solve the problems of data memory and program memory multiplexing, affecting the data throughput rate of the pipeline, and the instruction set is not scalable, and achieves efficient processing. Effect

Inactive Publication Date: 2004-07-28
SHANGHAI EASTSOFT MICROELECTRONICS
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Problems solved by technology

[0004] These characteristics of RISC microcontrollers also bring some essential defects and deficiencies: (1) The instruction set cannot be expanded; (2) There are many pipeline segments and stages, which brings the complexity of data correlation criteria in pipeline segments , sometimes even affects the data throughput of the pipeline; (3) the data memory and the program memory are multiplexed

Method used

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  • New-type RISC pieline microcontroller structure and its operation method
  • New-type RISC pieline microcontroller structure and its operation method
  • New-type RISC pieline microcontroller structure and its operation method

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Embodiment Construction

[0059] The hardware details associated with the functional features of the microcontroller architecture are described in detail below.

[0060] Such as Figure 10 It is a two-stage four-stage pipeline structure, driven by a four-phase clock, and each section of the pipeline completes the function in the corresponding clock phase, and it includes: an address fetching and decoding device 80, which is used to fetch instructions from the program memory 2 and decode them Operation, it includes instruction decoder 32, multiplexer 75, program counter 27, program memory 2; Read register device, for reading data from working register 36 and data register 1, it includes data memory 1, working register 36 Arithmetic logic operation device (ALU 37) 82, used for arithmetic and logic operations; Write-back register and internal interrupt and stack processing device 83, for ALU operation result is written back in the register, carries out internal interrupt and stack processing simultaneousl...

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Abstract

The present invention relates to a new-type RISC microcontroller frame, its core has two-level pipeline, and its adopts data memory and instruction memory separated Hafford-type structure, its access speed can be increased by once, its instruction set has 38 instructions, coding efficiency is high, it adopts pipeline structure, and it is easy to make instruction extension, said microcontroller frame can support low-power sleeping and wake-up mode, can support external interruption and support B port high-4-bit change interruption, and has strong interruption processing capacity, it can process 8-level interruption. Its data memory adopts single-port asynchronous low power consumption SRAM, storage depth is 256X8, can be extended to 2K, the program memory adopts embedded FLASH, storage depth is 4Kx16 bit, can be extended to 64 K bit, its addressing mode has direct addressing, indirect addressing and immediate number addressing mode, can be operated at DC-40 MHz.

Description

technical field [0001] The present invention generally belongs to the field of microcontrollers (MCUs) in the field of semiconductor integrated circuit design, and specifically is a microcontroller that executes a reduced instruction set. Background technique [0002] With the continuous improvement of deep submicron CMOS integrated circuit production technology, it is now technically possible to integrate complex microcontroller (MCU) cores on a chip, while leaving enough silicon chip area for implementing complex memories and Peripheral logic, design methodologies and architectures that used to be used in high-end 32-bit and 64-bit CPUs can now be effectively used in low-cost 8-bit microcontroller systems. With these powerful and inexpensive microcontrollers, the level of overall system integration continues to increase. The hardware structure can execute more complex and efficient programs and integrate more hardware functions. [0003] In recent years, the Reduced Inst...

Claims

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Application Information

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IPC IPC(8): G06F9/22G06F9/38G06F9/40
Inventor 朱建国潘松李逍波
Owner SHANGHAI EASTSOFT MICROELECTRONICS
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