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Method for concurrently forming silicon wafer suede and PN junction during solar cell manufacture

A solar cell, PN junction technology, applied in the direction of final product manufacturing, sustainable manufacturing/processing, circuits, etc., can solve the problems of low product qualification rate, easy to cause pollution, high manufacturing cost, shorten the process time, prevent workpiece pollution , The effect of simplifying the production line

Inactive Publication Date: 2007-03-28
SEMICON MFG INT (SHANGHAI) CORP +1
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AI Technical Summary

Problems solved by technology

Forming the textured structure on the surface of the P-type silicon wafer and performing phosphorus diffusion doping are two process steps, and are realized by two different equipments. Not only the process time is long, but also it is easy to cause pollution during the transfer process of the workpiece. Impurity diffusion is carried out at high temperature, and doping at high temperature requires extremely complicated control, resulting in low product yield and high manufacturing costs.

Method used

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Embodiment Construction

[0013] The method for forming textured structure and PN junction simultaneously on the surface of the P-type silicon chip of the present invention comprises the following process steps:

[0014] Step 1, silicon wafer surface cleaning treatment, the specific treatment conditions are, use 5±1% HF, add 5±1% HCL and the remaining amount of reverse osmosis water to form a mixed solution, and clean at room temperature for 5-6 minutes.

[0015] Step 2, low-temperature drying. The specific drying method is to dry with hot air at 60±5°C, and the drying time is 20±2 minutes.

[0016] Step 3, after the cleaning treatment, the silicon wafer is transported to the LPCVD furnace tube for processing, and a textured structure and a PN junction are formed on the surface of the silicon wafer at the same time. The processing conditions are: the vacuum degree in the furnace tube is kept at 100-300 millitorr, preferably The vacuum degree is 100 millitorr (mTorr), the temperature range is 520°C-580°...

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Abstract

Using method of low pressure chemical vapor deposition (LPCVD) creates coarse structure of pile fabrics composed of thin layer of semisphere silicon crystal grains, and carries out N type impurity diffusion at low temperature (ex. phosphorus diffusion) to form N trap, PN junction in P type silicon chip on surface of silicon chip at same time.

Description

technical field [0001] The invention relates to a method for manufacturing a solar cell, in particular to a method for simultaneously forming a textured surface of a silicon wafer and a PN junction in the manufacture of a solar cell Background technique [0002] In the solar cell manufacturing method, first, anisotropic etching is carried out on the P-type silicon wafer used as the raw material of the solar cell, and a textured structure is formed on the surface of the silicon wafer; then, phosphorus is diffused to form an N-well, thereby forming a PN junction. Due to the grain size distribution and orientation, the texture structure formed on the surface of the silicon wafer is random, and the conversion efficiency of the solar cell is very sensitive to these two process steps due to the diffusion doping at a relatively high temperature. Forming the textured structure on the surface of the P-type silicon wafer and performing phosphorus diffusion doping are two process step...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/18
CPCY02P70/50
Inventor 衣冠君苏晓平江彤
Owner SEMICON MFG INT (SHANGHAI) CORP
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