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HF vapor phase cleaning and oxide etching

a technology of oxide etching and vapor phase, which is applied in the direction of basic electric elements, semiconductor/solid-state device manufacturing, electrical equipment, etc., can solve the problems of critical contamination of high-temperature processing equipment, metal and other contamination can be trapped, and traditional aqueous cleaning processes are less effective or completely ineffective, etc., to achieve high efficiency, reproducibility, and precision

Inactive Publication Date: 2005-01-06
MASSACHUSETTS INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0014] The HF vapor processes of the invention enable all-dry semiconductor substrate cleaning, oxide etching, and etch residue removal, among other processes, which heretofore have conventionally required large volumes of aqueous chemicals that cannot be precisely controlled. All-dry vacuum cluster systems including chambers for the HF vapor processes of the invention, as provided by the invention, enable high efficiency, precision, and reproducibility for critical and frequent processes required of most microelectronic fabrication sequences.

Problems solved by technology

Metal and other contamination can be trapped in this native oxide layer and would critically contaminate high-temperature processing equipment.
Now, however, as microelectronic features shrink to the sub-micron regime, as the aspect ratio of wafer topology greatly increases, and as the number of microelectronic metal interconnect layers is increased, traditional aqueous cleaning processes are less effective or completely ineffective.
Thorough drying of rinse solutions from around and in small or high aspect ratio features can be difficult and can result in trapping of contamination at those features.
Furthermore, new combinations of microelectronic materials and new exotic microelectronic materials can be adversely affected by aqueous cleaning chemicals that historically were considered benign to more conventional materials.
Aside from structure and materials considerations, it is found that microfabrication process facilities are under increasing pressure to reduce the volume of waste chemicals they generate.
HF vapor cleaning and etching has not been fully adopted for cleaning and etching steps in microelectronic fabrication processing, however, due to unwanted contamination that can be introduced by a vapor process itself, and due to a lack of clear understanding of the mechanisms and operational regimes of vapor-based wafer cleaning and etching, with a resulting inability to precisely control the processes.
For example, it has been found that under some process conditions, liquid phase condensation of vapor phase reactants on a wafer can occur during a cleaning or etch process, and that high concentrations of reaction products in this condensed phase can result.
But more fundamentally, the introduction of additional contaminants by a vapor process intended for contaminant removal renders the vapor process inefficient and ineffectual.
The lack of etch control of which this pitting is a symptom that is generally considered to disqualify the vapor etch process for microfabrication steps requiring high-precision.
Beyond the particular concerns of lack of process uniformity control and unwanted process contamination described above, it has historically been considered extremely difficult to guarantee HF vapor process repeatability or predictability with respect to starting wafer conditions such as contamination conditions.

Method used

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  • HF vapor phase cleaning and oxide etching
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Examples

Experimental program
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Effect test

example 1

[0057] The process parameters of a vapor-phase HF process for etching an oxide layer of about 540 nm in thickness, grown by thermal oxidation on a silicon wafer was carried out to identify the process conditions corresponding to the condensed regime and the uncondensed multilayer, monolayer, and sub-monolayer regimes described above. A silicon wafer was processed in the system of FIG. 1 and by the procedure described above. The wafer temperature was held at about 40° C., and the partial pressure of water vapor was held at about 5.4 T. The partial pressure of HF vapor was slowly increased over time. As the partial pressure of the HF vapor was increased, real time ellipsometric measurements were taken of the reactants forming on the oxide layer surface.

[0058] Referring to FIG. 3A there is shown a plot of the measured spectroscopic ellipsometric signal at a wavelength of about 4502 Å as the partial pressure of the HF vapor was increased. FIG. 3B is a plot of measured and calculated el...

examples 2-3

[0061] A layer of oxide of about 5500 Å in thickness, grown by thermal oxidation on a silicon wafer was etched following the HF vapor etch procedures given above, with the conditions set such that the etch was carried out in a noncondensed regime. FIG. 4A is a plot of ellipsometric spectroscopic signal for a wavelength of 4502 Å taken during the etch process. As the thickness of the oxide layer decreased due to the etch, the signal increased in an expected manner. The etching process was stopped at 3 min after etching about 300 Å of the oxide.

[0062] A layer of thermal oxide of about 5500 Å in thickness was also etched following the HF vapor etch procedures given above, here with the conditions set such that the etch was carried out in the condensed regime. FIG. 4B is a plot of ellipsometric spectroscopic signal for a wavelength of 4502 Å taken during the etch process. As the thickness of the oxide decreased and the condensed layer is formed, the measured signal displayed the charac...

examples 4-8

[0064] The impact of temperature and pressure on oxide etch rate was measured for HF vapor processes carried out in the sub-monolayer, monolayer, and multilayer noncondensed regimes to further characterize the distinctions between the three regions. Referring to the Arrhenius plot of FIG. 5, vapor HF oxide etches were carried for a range of temperatures and for five different partial pressure conditions. Each of the wafers was subjected to a pre-etch step in which a positive charge was produced on the oxide layer. Details of this charging step and its impact on the etch characteristics are provided below.

[0065] In all cases, a layer of thermal oxide of a thickness of about 5500 Å was exposed to the etch conditions for about 6 min. The total gas flow rate for all of the etch processes was set at 500 sccm. For the cases where the HF vapor partial pressure was 20 T, 15 T, or 1 T and the water vapor partial pressure was 8 T, 6 T or 4 T, respectively, the total pressure was 125 T. For t...

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Abstract

HF vapor processes are provided for etching oxide on a semiconductor substrate, cleaning a substrate, or cleaning a metal structure on a substrate. In the processes, a semiconductor substrate to be cleaned or having oxide to be etched is exposed to anhydrous hydrofluoric acid vapor and water vapor at a substrate temperature greater than about 40° C. Control of substrate temperature, hydrofluoric acid vapor pressure and water vapor pressure inhibits formation of liquid on the substrate and forms on the substrate a sub-monolayer of etch reactant and product molecules by adsorption of etch reactant and product molecules at less than about 95% of oxide adsorption sites.

Description

[0001] This application is a continuation of prior copending U.S. nonprovisional application Ser. No. 09 / 498,303, filed Feb. 4, 2000, the entirety of which is incorporated by reference, which claims the benefit of U.S. provisional Application No. 60 / 118,937, filed Feb. 5, 1999, the entirety of which is incorporated by reference.BACKGROUND OF THE INVENTION [0002] This invention relates to processes for cleaning silicon substrates such as silicon wafers and for etching oxide layers on such wafers, and more particularly relates to wafer cleaning and oxide etching techniques employing hydrofluoric acid. [0003] The effectiveness of cleaning processes for removing contamination from silicon wafers employed for microfabrication is growing ever more important as the critical size of microfabricated electronic devices shrink. Wafer contamination is generally introduced from wafer production and packaging, from exposure to the ambient, and from human exposure during processing, and can consis...

Claims

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Application Information

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IPC IPC(8): H01L21/306H01L21/311
CPCH01L21/31116H01L21/02049
Inventor HAN, YONG-PILSAWIN, HERBERT H.
Owner MASSACHUSETTS INST OF TECH