Method for applying metal features onto metallized layers using electrochemical deposition using acid treatment

Abstract

The present invention is directed to a process for producing structures containing metallized features for use in microelectronic workpieces. The process treats a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and metallized features according to the invention include an acid treatment of the barrier layer, an electrolytic treatment of the barrier layer, or deposition of a bonding layer between the barrier layer and metallized feature. The present invention thus modifies an exterior surface of a barrier layer making it more suitable for electrodeposition of metal on a barrier, thus eliminating the need for a PVD or CVD seed layer deposition process.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of U.S. application Ser. No. 10 / 470,287, filed Jul. 22, 2003, which is the National Stage of International Application No. PCT / US03 / 00890, filed Jan. 10, 2003, which claims the benefit of U.S. Application No. 60 / 347,520, filed Jan. 10, 2002.FIELD OF THE INVENTION [0002] The present invention is directed to methods for forming metallized structures on barrier layers through electrochemical deposition. BACKGROUND OF THE INVENTION [0003] In the fabrication of microelectronic devices, application of one or more metallization layers is an important step in the overall fabrication process. The metallization may be used in the formation of discrete microelectronic components, but is most often used to provide interconnect components formed on a workpiece, such as a semiconductor wafer. For example, metallized structures are used to interconnect devices of an integrated circuit. [0004] An integrated circuit is ...

AI Technical Summary

Benefits of technology

[0013] The present invention is directed to processes for forming structures containing metallized features for use in microelectronic workpieces, wherein the metallized features are electrochemically deposited onto a barrier layer in the absence of a CVD or PVD deposited seed layer. The processes of the present invention allow integrated circuit manufacturers to reduce their costs and increase their throughput by avoiding expensive and time-consuming CVD or PVD methods for depositing seed layers.

[0015] In one aspect of the present invention, a barrier layer is provided on a dielectric feature that is carried by a surface of a microelectronic workpiece. The barrier layer separates the underlying dielectric feature from metallized features that are to be formed on the barrier layer. In accordance with the present invention, the barrier layer is modified by electrolytically treating it before electrochemically depositing a metallized feature, such as seed layer or gap-fill metallization. By modifying the surface of the barrier layer, adhesion between the barrier layer and the electrochemically deposited metallized feature is improved and peeling of the deposited metallized feature from the barrier layer due to subsequent processing steps such as rinsing and drying is reduced or avoided.

[0016] In another aspect of the present invention, the barrier layer overlying a dielectric feature is modified by treating the surface of the barrier layer with an acid. The surface of the barrier layer after the acid treatment exhibits improved adhesion to a metallized feature subsequently deposited onto the surface of the barrier layer. The improved adhesion helps the subsequently deposited formed structure avoid delamination when it is subjected to subsequent processing steps such as rinsing and drying.

[0019] The processes of the present invention provide an attractive alternative to processes that deposit seed layers using PVD or CVD. By avoiding the costs associated with PVD and CVD, integrated circuit manufacturers will be able to produce their products more cost-effectively. The present invention will also allow integrated circuit manufacturers to increase their throughput by avoiding time-consuming PVD or CVD used to deposit seed layers. By improving the adhesion between barrier layers and metallized features formed over the barrier layers, delamination between the metallized features and the barrier layer as a result of subsequent processing steps is reduced. Integrated circuit manufacturers will find this desirable as it will increase production yields and produce more reliable devices.

Problems solved by technology

Despite the advantages of copper, it has not been as widely used as an interconnect material as one would expect.

This is due, at least in part, to the difficulty in effectively and economically depositing copper metallization.

Unfortunately, materials used as barrier layers typically do not exhibit the electrical conductive properties necessary to allow for the uniform electrochemical deposition of copper directly onto the barrier layers using conventional gap fill chemistries and processes.

CVD can result in conformal copper coverage over a variety of topological profiles; however, CVD is expensive to carry out and utilizes expensive equipment.

One disadvantage of PVD is that it may result in poor (nonconformal) step coverage when used to fill recessed micro-structures, such as vias and trenches, disposed in the surface of the semiconductor workpiece.

In addition, both PVD and CVD are considered to be relatively slow, thus adversely affecting manufacturing throughput.

However, it has been observed by the present inventors that electrochemical deposition of copper directly onto untreated barrier layers leads to unsatisfactory results, such as poor nucleation and copper peeling due to poor adhesion between the electrodeposited copper and the material of the barrier layer.

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