Pre-treatment to eliminate the defects formed during electrochemical plating

a technology of electrochemical plating and pretreatment, which is applied in the direction of superimposed coating process, vacuum evaporation coating, coating, etc., can solve the problems of increasing the current density of such features, not consistently filling structures with narrow openings or difficult aspect ratios, and forming voids in conductors. , to achieve the effect of improving wettability, reducing void defects, and high ra

Inactive Publication Date: 2007-04-12
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0014] Embodiments of the invention generally provide methods for reducing the formation of void-type defects on the surface of a substrate during electrochemical processing. More particularly, embodiments of the invention provide methods to improve the wetting of a substrate surface prior to immersion and thereby minimize adhesion of bubbles to the substrate surface during substrate immersion.
[0015] In one embodiment, a thin, uniform metal oxide is formed on the surface of the substrate immediately prior to immersion of the substrate to improve wetting of the substrate by the plating solution. In one aspect, the metal oxide is formed by exposing the substrate to an oxygen-containing gas, e.g., air, for several hours. No forced convective flow is used. In another aspect, the metal oxide is formed by flowing an oxygen-containing gas over the surface of the substrate. In yet another aspect, the metal oxide is formed by rotating the substrate at a relatively high rate in the presence of an oxygen-containing gas.
[0017] In another embodiment, an optimized substrate immersion method involving a first tilt angle and a second tilt angle is used in conjunction with a substrate with improved wettability to further reduce void defects. The procedure is designed to immerse a substrate into a plating solution with minimal bubble formation. In one aspect, the metal oxide layer is formed by exposure to an oxygen-containing gas while the substrate is rotated at a relatively high rate. In another aspect, the substrate is initially stripped of any metal oxides by an anneal process in a hydrogen-enriched environment. In another aspect, the wettability of the substrate surface is improved by exposing the substrate to an oxygen-containing gas with no forced convective flow for several hours.

Problems solved by technology

Many conventional deposition processes do not consistently fill structures with narrow openings or difficult aspect ratios.
Additionally, as the feature widths decrease, the device current typically remains constant or increases, which results in an increased current density for such features.
Aluminum can also suffer from electromigration, leading to the formation of voids in the conductor.
However, as the interconnect sizes decrease and aspect ratios increase, void-free interconnect feature fill by conventional metallization techniques becomes increasingly difficult using CVD and / or PVD.
Research has shown that one cause of void-type plating defects is the presence of air bubbles on the surface of the substrate being plated.
This forms a void-type defect in the plated layer.
These processes have not been reliable or completely effective in removing the void-type defects seen on the substrate.
Such void-type defects formed in the ECP deposited layer may affect the yield and electromigration results and are a real concern to electronic device manufacturers.

Method used

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  • Pre-treatment to eliminate the defects formed during electrochemical plating
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  • Pre-treatment to eliminate the defects formed during electrochemical plating

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Embodiment Construction

[0032] Embodiments of the invention generally provide various methods for processing a substrate to reduce the number of void-type defects formed on the substrate when an electrochemical plating process is performed on the substrate. The method of the invention is designed to minimize plating defects by performing one or more preprocessing steps on a substrate prior to performing the ECP process.

[0033]“Plating” as used herein, refers to any deposition process that includes electrochemical plating, electroless plating, or a combination of both.

[0034] Percent concentrations of gas mixtures, as used herein, refer to volume percent.

[0035]“Ambient air” as used herein, refers to air that contains about 21% O2 (by volume). For example, a volume of air that has been sealed in a container that also contains substances that spontaneously react with the gaseous oxygen therein, such as un-oxidized copper, is not considered “ambient air” after any significant period of time has elapsed. This ...

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Abstract

Embodiments of the invention provide methods for reducing formation of void-type defects on the surface of a substrate during electrochemical plating. Embodiments of the invention provide methods to improve the wetting of a substrate surface prior to immersion and thereby minimize adhesion of bubbles to the substrate surface during immersion. A thin uniform metal oxide is formed on a metal layer on the substrate immediately prior to substrate immersion. In one aspect, exposing the substrate to an oxygen-containing gas, e.g. air, forms the metal oxide. The oxygen-containing gas may be flowed over the substrate or the substrate may be rotated at a high rate in the presence of an oxygen-containing gas. In another aspect, non-uniform metal oxides are first removed from the substrate in an anneal process and a thin uniform metal oxide is subsequently re-formed. An optimized substrate immersion method may also be used to further reduce void defects.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] Embodiments of the invention generally relate to a method for processing a semiconductor substrate to reduce defects formed during an electroplating process. [0003] 2. Description of the Related Art [0004] Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor devices. The multilevel interconnects that lie at the heart of this technology require the filling of contacts, vias, lines, and other features formed in high aspect ratio apertures. Reliable formation of these features is very important to the success of both VLSI and ULSI as well as to the continued effort to increase circuit density and quality on individual substrates and die. [0005] As circuit densities increase, the widths of contacts, vias, lines and other features, as well as the dielectric materials between them, ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): C23C28/00C25D5/34
CPCC23C14/16C23C14/5853C23C28/023C25D5/34H01L21/288H01L21/2885H01L21/76856H01L21/76873H01L21/76874C23C28/322C23C28/345C25D7/123
Inventor GU, HAIYANGYANG, JEFFWEE, HO SUNXI, MINGMORI, GLEN T.ZONDAK, YOHAN
Owner APPLIED MATERIALS INC
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