CDMA power amplifier design for low and high power modes

Abstract

An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates generally to the field of power amplifiers in multi-band communication systems. More particularly, the present invention relates to circuitry associated with such power amplifiers, such as harmonic filters, impedance load switching circuits, pre-distortion phase filters, and the like. [0003] 2. Description of the Related Art [0004] Several digital air interface standards have been developed for providing efficient digital communication of voice, data, fax and text messages under the umbrella of “personal communications services” or PCS. Operational PCS systems, such as systems based on the GSM TDMA (Time Division Multiple Access) or IS-95 CDMA (Code Division Multiplex Access) air interface standards, are being implemented in the United States in the 1900 MHz frequency range. Meanwhile, existing analog (AMPS) and digital (D-AMPS) at 800 MHz cellular systems continue to operate. Thus, the...

AI Technical Summary

Benefits of technology

The present invention provides a variable load circuit for an amplifier that can adjust its impedance based on the power mode of the amplifier. This allows for improved efficiency performance at lower output power levels. The load circuit can adjust its impedance by using a low impedance state for high power operation and a high impedance state for low power operation. The load circuit can also include a harmonic filter to remove harmonics and correct signal distortion. The amplifier circuit can provide high efficiency in both the low power mode and the high power mode. The use of a single or multiple switches can be used to implement the load circuit. The power mode signal can be a low power mode signal or a high power mode signal. The amplifier circuit can also include a phase shift circuit to improve performance.

Problems solved by technology

An undesirable side effect of providing this low impedance is that it often leads to a degraded efficiency when the output power level is low.

The power amplifiers in these devices, however, are optimized for the high power mode with the low power mode operations, when present, being relatively inefficient.

Such improvement at high power levels, however, also results in reduced average power efficiency due to reduced efficiency in the low power mode, which was noted to be the mode in which 95% of time was spent by CDMA sets.

Thus, the typical design of power amplifiers, although optimized for high power mode, actually results in reduced battery life.

The prior art does not teach or suggest selecting the output matching impedance to improve operation at an output power levels other than at high power even though CDMA phones actually spend an overwhelming amount of their operational time in relatively lower power modes.

The high power performance of a power amplifier is often compromised by the distortion or noise generated as a result of such an operation.

Using a predistortion linearizer adversely impacts the performance in lower power modes due to the weak input signals.

Such limitations on the use of predistortion linearizers require that a choice be made between superior performance in a high power mode and the performance in a lower power mode.

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