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Ashing Method And Ashing Apparatus

a technology of ashing apparatus and ashing method, which is applied in the field of ashing device, can solve the problems of reducing the processing capacity of plasma processing equipment, affecting the processing efficiency of instruments, and easily degrading the film properties, so as to achieve the effect of reducing the amount of h radical that reaches the wafer, and improving the peeling residual without prolonging the processing tim

Inactive Publication Date: 2008-06-05
SHIBAURA MECHATRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides an ashing device and method that can effectively remove resist from a wafer while maintaining the film properties of a low-K film. By using a gas blend of H2 and inert gas as the ashing gas, the ashing rate can be increased while reducing the dielectric constant. The addition of H2O or O2 to the inert gas can further enhance the ashing process. The positional relationship between the processing subject and the plasma generating chamber can also be adjusted to minimize the impact of ultraviolet rays on the processing subject. Overall, this invention provides a more efficient and effective method for ashing wafers.

Problems solved by technology

In particular, interlayer insulating films which use porous materials with a low relative dielectric constant have a plurality of fine air voids which are exposed (large relative surface area), so the resistance to highly reactive oxygen plasma is extremely low, the film properties are easily degraded, and the degradation due to oxygen plasma is very significant.
With the wafer ashing process when the aforementioned Low-K film is used as an interlayer insulation film, removing the resist by conventional ashing using oxygen (O2) plasma is not suitable, so ashing gas conditions that are completely different from conventional are required, and plasma processing has been performed using hydrogen (H2), nitrogen (N2), or ammonia (NH3) and the like.
However, there are problems with the processing capability of the plasma processing equipment when these ashing gas conditions are used.
Furthermore, with a gas blend of gases containing hydrogen and gases containing fluorine according to Patent Reference 2, there is a dramatic increase in the dielectric constant and the film properties may be degraded.

Method used

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Examples

Experimental program
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first embodiment

[0032]The ashing device of the present embodiment provides a process chamber 2 which is a vacuum chamber 1 inside a vacuum chamber 1 as shown in FIG. 1. A support stand 3 is provided in the process chamber 2, and the processing subject S is placed on the support stand 3. Note, the support stand 3 has a temperature control mechanism not shown in the drawings, and the temperature of the processing subject S can be controlled by this temperature control mechanism. The processing subject includes silicon wafers for manufacturing semiconductor devices and glass substrates for liquid crystal display devices.

[0033]An exhaust port 5 is formed in the bottom plate 4 of the vacuum chamber 1, and an exhaust pipe 6 connected to a vacuum pump (not shown in the drawings) on one end is attached to the exhaust port 5. Furthermore, a gas injection port 8 is formed in the center of the upper lid 7 which forms the top plate of the vacuum chamber 1, and a gas injection pipe 9 made of a fluorine based re...

second embodiment

[0048]The ashing device according to the second embodiment adds a change to the composition of ashing gas that is injected from the gas regulator 20 in the first embodiment. Specifically, a composition where between 0.01% and 0.1% O2 or between 1% and 5% H2O is added to the H2 and He gas blend. Note, other components are similar to the aforementioned first embodiment and have been omitted from the description.

[0049]With a resist ashing process where a Low-K film is exposed on the processing subject S (wafer), peeling residue occurs after ashing in a process where an H2 and He gas blend is used as the ashing gas. If the plasma generating chamber member 10 is made from SiO2 as described above, when a gas containing H2 is supplied from the gas regulator 20 and the hydrogen plasma is excited in the plasma generating chamber 14 over a discharge time of several tens of hours, the SiO2 that forms the plasma generating chamber member 10 will be reduced to Si. When the SiO2 is converted to S...

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Abstract

An ashing device and ashing method that can positively remove resist from a wafer while preventing degradation of the film material properties of exposed porous Low-K film on the wafer. The ashing device of the present invention introduces a gas to a dielectric plasma generating chamber 14, excites said gas to generate a plasma, and performs plasma processing using said gas plasma on a processing work S in use of a Low-K film. The ashing gas introduced from a gas regulator 20 is an inert gas to which H2 has been added. The configuration is formed so that plasma is generated from the gas blend, and the resist is removed by the hydrogen radicals generated.

Description

TECHNICAL FIELD[0001]The present invention relates to an ashing device for peeling photoresist that is used as a mask when making a circuit on a wafer in a semiconductor wafer process, and more particularly to technology to prevent reduction of the ashing rate and increase the life of a plasma generating chamber member.BACKGROUND TECHNOLOGY[0002]LSI (Large Scale Integration) circuits are semiconductor integrated circuits which have over 1000 elements, and ULSI or the like are those which have over one million elements stored on a single chip, and in recent years, 100 million or more elements have been formed on a single chip.[0003]This type of ULSI cannot be accommodated simply by miniaturizing elements on a plane, so multiple layer wiring construction with a plurality of overlapping layers of wiring has become essential. A multiple layer wiring construction increases the capacitance between layers and causes the elements to have longer signal delay times, so in order to reduce the ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/3065
CPCH01L21/31138G03F7/427H01L21/304H01L21/306H01L21/3065
Inventor YAMAZAKI, KATSUHIRO
Owner SHIBAURA MECHATRONICS CORP