SEMICONDUCTOR DEVICE COMPRISING METAL-BASED eFUSES OF ENHANCED PROGRAMMING EFFICIENCY BY ENHANCING METAL AGGLOMERATION AND/OR VOIDING

a technology of efuses and metal agglomeration, applied in the direction of heat/cooling contact switches, information storage, instruments, etc., can solve the problems of considerable consumption of valuable chip area, and achieve the effect of reducing compressive stress

Inactive Publication Date: 2011-06-30
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0025]One illustrative method disclosed herein relates to electrically programming a fuse in a semiconductor device. The method comprises establishing a current flow in a fuse body of the fuse to initiate a current-induced metal diffusion. The method further comprises reducing a compressive stress in the fuse body, wherein the compressive stress is caused by the current-induced metal diffusion.

Problems solved by technology

To this end, the present disclosure considers the incorporation of efficient stress-reducing mechanisms for reliably inducing an electromigration effect, i.e., a significant migration or diffusion of metal atoms and ions in the fuse body, while the overall dimensions, and in particular the effective length, of the fuse body may be reduced compared to conventional approaches in which, for a given cross-sectional area and material composition of a metal line, the length thereof may be increased to be well above the Blech length, which, however, may result in a considerable consumption of valuable chip area.

Method used

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  • SEMICONDUCTOR DEVICE COMPRISING METAL-BASED eFUSES OF ENHANCED PROGRAMMING EFFICIENCY BY ENHANCING METAL AGGLOMERATION AND/OR VOIDING
  • SEMICONDUCTOR DEVICE COMPRISING METAL-BASED eFUSES OF ENHANCED PROGRAMMING EFFICIENCY BY ENHANCING METAL AGGLOMERATION AND/OR VOIDING
  • SEMICONDUCTOR DEVICE COMPRISING METAL-BASED eFUSES OF ENHANCED PROGRAMMING EFFICIENCY BY ENHANCING METAL AGGLOMERATION AND/OR VOIDING

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Embodiment Construction

[0039]Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0040]The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details ...

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Abstract

Metal fuses in semiconductor devices may be formed on the basis of additional mechanisms for obtaining superior electromigration in the fuse bodies. To this end, the compressive stress caused by the current-induced metal diffusion may be restricted or reduced in the fuse body, for instance, by providing a stress buffer region and/or by providing a dedicated metal agglomeration region. The concept may be applied to the metallization system and may also be used in the device level, when fabricating the metal fuse in combination with high-k metal gate electrode structures.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming electronic fuses for providing device internal programming capabilities in complex integrated circuits.[0003]2. Description of the Related Art[0004]In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are decreased with the introduction of every new circuit generation, to provide currently available integrated circuits with an improved degree of performance in terms of speed and / or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size of the trans...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01H37/76
CPCG11C17/16H01L2924/3011H01L23/5256H01L2924/0002H01L2924/00
Inventor POPPE, JENSAUBEL, OLIVERHENNESTHAL, CHRISTIANPAGEL, HOLGERKURZ, ANDREAS
Owner GLOBALFOUNDRIES INC
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