BEOL integration scheme for copper CMP to prevent dendrite formation

Abstract

Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices by performing a copper deposition process to fill the trench or via with copper, which can be performed by fill, plating or electroless deposition. Copper clearing of copper overburden is performed using CMP to stop on an existing liner. Copper in the trenches or vias is recessed by controlled etch. An Nblok cap layer is deposited to cap the trenches or vias so that copper is not exposed to ILD. Nblok overburden and adjacent liner is then removed by CMP. Nblok cap layer is then deposited. The proposed approach is an alternative CMP integration scheme that will eliminate the exposure of copper to ILD during CMP, will prevent any dendrite formation, can be used for all metal layers in BEOL stack, and can be utilized for multiple layers, as necessary, whenever copper CMP is desired.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming copper-based conductive structures using a chemical mechanical planarization (CMP) integration scheme that eliminates exposure of copper to interlayer dielectric (ILD).[0003]2. Description of the Related Art[0004]The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that, to a great extent, substantially determines the performance capability of integrated circuit devices employing such transistors. A field effect transistor, irrespective of whether an NMOS tr...

AI Technical Summary

Benefits of technology

The proposed approach is a way to integrate copper into a semiconductor device without causing any damage to the underlying layers. This approach prevents the formation of dendrites, which can cause problems in the manufacturing process. It can be used for all metal layers in the device, and can be applied to multiple layers if copper chemical mechanical polishing is needed. Overall, this approach improves the reliability and efficiency of semiconductor manufacturing.

Problems solved by technology

However, the ongoing shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by reduction of the device features.

Upon decreasing channel length, however, the pitch between adjacent transistors likewise decreases, thereby limiting the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as contact vias and the like—that may fit within the available real estate between adjacent transistors.

Accordingly, the electrical resistance of conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is correspondingly decreased.

However, the use of copper metallization systems with such low-k dielectric materials can be problematic.

This residual copper can result in formation of dendrites due to copper oxidation.

The presence of water will accelerate the dendrite growth which becomes a bigger problem for low-k ILD because it is porous and holds moisture.

The dendrite can result in connecting copper lines resulting in shorting, capacitance and Time Dependent Dielectric Breakdown (TDDB) issues.

However, the queue time needs to be short, for example less than 6 hours.

However, the short queue time needed is not ideal or practical for high volume manufacturing.

However, the use of such chemicals adds steps, complexity and cost to the manufacturing process.

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