Process for chemical vapor phase depositing titaniam nitride containing silicon using titanium containing organic metal material

Abstract

The CVD process of depositing TiSiN film for integrated circuit manufacture includes He carrying of Ti containing TDMA and Si containing trimethyl silane or SiCH4, heat decomposition to deposit TiSiN film, and in-situ RE H2-N2 plasma treatment. The TiSiN film thus deposited has excellent step coverage and homogeneous resistance and film thickness. The TiSiN film forms Cu diffusion barrier with stable physical and chemical performance, and can prevent the diffusion of F ion in low dielectric coefficient material. TiSiN has also one characteristic that it has adhesion with both Cu metal film and porous low dielectric coefficient medium, and this is favorable to raising the electric migration resistance to Cu interconnection metal, and is suitable for multilayer Al wiring process and Cu metal Damascus interconnection process.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a method of using titanium-containing organometallic material TDMA and adding 3-methylsilane (3MS) or adding a small amount of silane (SiCH 4 ), a process of chemical vapor deposition of a titanium-containing silicon nitride TiSiN diffusion barrier layer. Background technique [0002] With the continuous reduction of integrated circuit design rules, the line width of the feature size has been reduced to 0.10 microns, and the trend of continuous downward reduction is maintained. On the other hand, the density of devices in integrated circuits continues to increase, the number of metal wiring layers is increasing, and the number of wiring layers in logic circuits has reached 7-8 layers. Due to the increase of the resistance of the metal interconnection line itself and its parasitic capacitance, the resulting RC interconnection dela...

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Problems solved by technology

Moreover, due to the shadow effect, the limitation of physical deposition lies in the uniformity of deposition, especially in thin lines and deep vias, the sidewall step coverage is very low, even with ion physical deposition (IPVD) method, when the substrate is biased with an electric field, the coverage of the sidewall and bottom is still very low

As a result, during the subsequent Cu plating, voids will appear in the through holes or even on the side walls of the wiring grooves, which will affect the yield and reliability of integrated circuits

[0010] On the other hand, in the technology of 0.13 microns and below, low dielectric constant (Low-κ) materials are mostly used as intermetallic dielectrics. Porous low dielectric constant (Low-κ) materials have rough surfaces, unstable chemical properties, and physical precipitation. The product method is not compatible with porous low dielectric constant (Low-κ) materials. At the technical stage below 0.10 microns, Cu is used as a wire material, and low dielectric constant (Low-κ) is used as an insulating medium between metal layers. Barrier layer deposited by chemical vapor deposition (CVD) with superior conformal properties

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