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Preparation method of NROM flash unit

A flash memory unit, N-type technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve problems such as consumption, large leakage current, and large additional power consumption

Inactive Publication Date: 2009-03-11
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, during the programming process, the drain terminals of all cells 10 that have the same bit line j as the selected cell will also be biased to a high voltage of 5V. ) and the surface punch-through effect will cause a large leakage current Ileak, resulting in a large additional power consumption
Third, high programming voltage will hinder the increase of memory chip density
Moreover, peripheral circuits also consume a lot of power in order to generate high voltage
Fourth, the high operating voltage will also directly affect the shrinkage of the core memory array
In the actual programming process, both the drain terminal and the control gate are connected to a high voltage. Due to this compromise, the efficiency of hot electron injection is low.
In addition, the generation and injection of hot electrons occur near the drain end, and the generated hot electrons have a high probability of being swept to the drain end instead of being injected into the silicon nitride layer, making the CHEI injection efficiency relatively low

Method used

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  • Preparation method of NROM flash unit
  • Preparation method of NROM flash unit
  • Preparation method of NROM flash unit

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Embodiment 1

[0108] Embodiment 1: A heterogeneous gate NROM flash memory cell

[0109] Such as Figure 4 As shown, in the flash memory cell of this embodiment, the silicon substrate 1 is p-type, the drain terminal 2 and the source terminal 7 are both N+ doped, and the gate stack adopts a tunnel oxide layer 3 / silicon nitride layer 4 / The structure of the oxide layer 6 is prevented. The control gate is divided into three regions, the middle region is P+ doped polysilicon 12 which is a high work function material, and both sides near the source and drain terminals are N+ type doped polysilicon 5 which is a low work function material. In this embodiment, near The lateral size ratio of N+ doped polysilicon at the source end and P+ doped polysilicon in the middle and N+ doped polysilicon near the drain end is 1:3:1.

[0110] A method for preparing the hetero-gate NROM flash memory is shown in FIG. 5, and the method is described in detail below:

[0111] (1) Using p-type single-polishing silicon subst...

Embodiment 2

[0116] Embodiment 2: a heterogeneous gate NROM flash memory cell

[0117] The flash memory cell of this embodiment is composed of a polysilicon control gate, source and drain regions, a tunneling oxide layer, a silicon nitride layer for storing data, and a blocking oxide layer. Different areas of the control gate are injected with different types of impurities, close to the control of the source and drain The gate is implanted with N-type impurities to form an N+ polysilicon control gate, and the middle control gate is injected with P-type impurities to form a P+ polysilicon control gate. A silicon oxide layer is separated between the N+ region where the N-type impurity is injected into the polysilicon control gate and the P+ area where the P-type impurity is injected into the polysilicon control gate, and a layer of nickel silicon is added to the polysilicon control gate to electrically connect the N+ polysilicon control gate and the polysilicon P+ region. .

[0118] The manufact...

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Abstract

A NROM flash storage unit is composed of control gate, source / drain region, tunneling oxidation layer, silicon nitride layer for storing data and blocking layer. It is featured as injecting different type of impurity into different region of control gate, injecting N type of impurity into control gate near source end and drain end to form N+ polysilicon control gate, injecting P type of impurity into control gate at middle to form P+ polysilicon control gate.

Description

Technical field [0001] The invention belongs to the technical field of non-volatile semiconductor memory, and relates to an NROM flash memory cell capable of improving programming efficiency and reducing programming voltage and an implementation method of its control gate. Background technique [0002] With the rapid development of portable electronic devices (such as mobile phones, digital cameras, MP3 players, PDAs, etc.), the requirements for data storage are getting higher and higher. Non-volatile memory has become the most important storage component in these devices because of its ability to save data even when the power is off. [0003] Compared with other non-volatile memory (such as ferroelectric memory, magnetic memory and phase change memory), because flash memory (Flash memory) can achieve a high chip storage density, and does not introduce new materials, manufacturing processes and current CMOS processes Compatible, therefore, it can be more easily and reliably integ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/788H01L29/43H01L21/336H01L21/28
Inventor 单晓楠黄如蔡一茂李炎周发龙
Owner SEMICON MFG INT (SHANGHAI) CORP
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