Production method of bulk silicon nano line transistor device

A technology of silicon nanowires and transistors, which is applied in the field of field effect transistor preparation, can solve the problems of small cross-section of source and drain regions, process complexity, and reduce device drive current, so as to reduce process manufacturing cost and have strong process controllability , Reduce the effect of parasitic resistance
CN101295677AActive Publication Date: 2008-10-29PEKING UNIV +1
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
PEKING UNIV
Publication Date
2008-10-29

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Abstract

The invention discloses a preparation method for a bulk silicon nanometer line transistor apparatus, which belongs to the technical field of manufacturing CMOS GSI (ULSI). The method realizes a bulk silicon nanometer line structure by an approach from up to down; a large amount of heat generated by the apparatus can be radiated from an underlay area by a source drain area, thus effectively restraining the self-heating effect of the apparatus. Besides, as the source drain of the bulk silicon nanometer line transistor apparatus is connected with the underlay, and a large fan-out deep source drain junction can be realized, thus effectively reducing a parasitic resistance and being capable of completely showing the advantages of the characteristics of a silicon nanometer line structure; the technique has high controllability and is compatible with the traditional technique technology. Compared with an SOI (Silicon on Insulator) silicon chip, the technique manufacture cost can be effectively reduced.
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Description

technical field

[0001] The invention belongs to the field of CMOS ultra-large-scale integrated circuit (ULSI) manufacturing technology, in particular to a method for preparing a field-effect transistor (Metal-Oxide-Silicon Field Effect Transistor, MOSFET). Background technique

[0002] In order to continuously reduce costs, increase integration, and improve performance in VLSI, the feature size of CMOS devices has been continuously reduced. However, when the size of the device is reduced to the deep submicron region, the leakage current of the device continues to increase, and the leakage-induced barrier lowering (DIBL) effect and the short channel effect become more and more obvious, which have become the main problems hindering the reduction of the device size. In order to overcome these problems, one of the effective ways is to propose a new device structure to improve the gate control ability of the device, improve the device characteristics, and better adapt to the smal...

Claims

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