2T embedded FLOTOX EEPROM

A read-only memory and embedded technology, applied in the direction of read-only memory, static memory, information storage, etc., can solve the problems of increasing the difficulty of the process, increasing the difficulty and cost of the process, increasing the complexity of the circuit, and the circuit layout area, etc., to achieve saving Die area effect

Inactive Publication Date: 2010-06-23
SHANGHAI HUA HONG NEC ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, it is necessary to provide NMOS transistors and PMOS transistors resistant to VPPH high voltage in the process, which increases the difficulty and cost of the process.
And in realizing the high-voltage charge pump (charge pump) circuit, since it is necessary to provide N tubes and P tubes resistant to VPPH high voltage, it also increases the difficulty of the process, increases the circuit complexity and the area of ​​the circuit layout, and improves the manufacturing process. cost

Method used

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  • 2T embedded FLOTOX EEPROM
  • 2T embedded FLOTOX EEPROM
  • 2T embedded FLOTOX EEPROM

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0016] like figure 2 As shown, the drain terminal of the storage transistor EE is connected as the bit line (Bitline) of the entire memory array, and the source terminal of the selection transistor N1 is used as the source line (Sourceline) of the entire memory array. Its operating voltage is shown in Table 2. When it is necessary to implement a write operation on the memory, a high voltage (VPPL) is applied to the bit line, and 0V is applied to the control gate (control gate) of the storage tube EE, so that The thin oxide layer of the storage tube occurs tunneling (tunneling), pulling electrons out of the floating gate (Floating gate), so that the storage tube is in the "1" state, and the power supply voltage is applied to the selection tube to ensure that it is turned on, and the source line is empty. (floating).

[0017] Table 2:

[0018]

[0019] To realize the erasing (erase) operation, apply high voltage to the control gate, add 0V to the bit line, and inject elect...

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Abstract

The invention discloses a 2T (2-transistor) embedded FLOTOX (floating gate tunnel oxide) EEPROM (electrically erasable programmable read only memory) characterized in that a selectron is located in the source area of a memotron in a memory cell. By arranging the selectron in the source area of the memotron, a memory array can achieve the operations of erasing and writing-in by only one high voltage. Therefore, the invention dispenses with the voltage peak-peak H (VPPH) and a circuit structure for generating the VPPH, and further reduces a high-voltage resistant component for generating and transferring the VPPH in the circuit, thereby dispensing with at least two layers of photomasks and various technological steps and saving the chip area.

Description

technical field [0001] The invention relates to a non-volatile memory in a semiconductor integrated circuit, in particular to a 2T embedded floating gate electrically erasable read-only memory in the semiconductor integrated circuit. Background technique [0002] like figure 1 As shown, in the structure of the current 2T floating gate electrically erasable read-only memory cell (FLOTOXEEPROM), the selection transistor is located at the drain region of the storage transistor, that is, the bit line (BIT LINE) is connected from the drain terminal of the selection transistor. The advantage of this is that the cells that do not have a selected row but are located in a selected column have the least erase interference. The disadvantage is that a VPPH greater than VPPL needs to be added to the gate of the selection transistor in the selected row to ensure that the gate voltage of the selection transistor is greater than the drain voltage, so that the selection transistor can be in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/04G11C16/06
Inventor 陈昊瑜陈广龙
Owner SHANGHAI HUA HONG NEC ELECTRONICS
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