Gain cell eDRAM for programmable logic device

Abstract

The invention belongs to the technical field of embedded dynamic random access memories (eDRAM), and in particular relates to a gain cell eDRAM for a programmable logic device. The gain cell eDRAM in the invention comprises a read MOS transistor, a write MOS transistor, a write word line, a read word line, a write bit line, a read bit line and an equivalent parasitic capacitor, wherein a charge storage end of the equivalent parasitic capacitor controls a switch tube of the programmable logic device; and by using the characteristic of non-destructive read or small destructive read of the gain cell eDRAM, the potential of a storage node does not change or the potential change is small when read operation is performed during updating operation, so the change of the logic state of the switch tube is not influenced. The chip area of the programmable logic device using the gain cell eDRAM can be greatly reduced.

Description

technical field [0001] The invention belongs to the technical field of embedded dynamic random access memory (eDRM), and in particular relates to a gain cell (Gain Cell) eDRAM used for a programmable logic device. Background technique [0002] PLD is the abbreviation of Programmable Logic Device, and FPGA is the abbreviation of Field Programmable Gate Array (Field Programmable GateArray). Ignoring the difference between the two, PLD and FPGA are collectively referred to as programmable logic devices. Programmable logic devices can complete the functions of any digital device, ranging from high-performance CPUs to simple 74 circuits, all of which can be implemented with PLDs. Programmable logic devices are like a piece of white paper or a pile of building blocks. Engineers can freely design a digital system through traditional schematic diagram input methods or hardware description languages. Through software simulation, the correctness of the design can be verified in adva...

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Problems solved by technology

[0006] However, the above figure 1 and figure 2 When the DRAM storage unit of the illustrated embodiment is applied to a programmable logic device, its main disadvantage is that the read operation is destructive, and the refresh operation is read first and then written, and the parasitic capacitance passes through the MOS gate during the read operation. Charge and discharge the parasitic capacitance (the read operation during the refresh operation is also destructive), at this time, due to the potential change of the parasitic capacitance, the state of the switch tube will change (conduction to off, or off to on, or conduction The degree of on-off becomes weaker), this change in the state of the switch will cause the logic state of the programmable logic device to be wrong

[0013] It

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