ESD (electrostatic discharge) protection circuit optimization method of RFIC (radio frequency integrated circuit) based on network S-parameter extraction

Abstract

The invention discloses an ESD (electrostatic discharge) protection circuit optimization method of an RFIC (radio frequency integrated circuit) based on network S-parameter extraction, and mainly solves the problems of poor accuracy and universality of the existing equivalent method and model construction method. The method mainly comprises the following steps: determining the parameters of an ESD protection device and a matching network of a port to be protected of the kernel RFIC; constructing a matching network with the ESD protection, and extracting S parameter through mixed-mode simulation; embedding the matching network into the kernel RFIC for optimized adjustment; returning and correcting the element parameters in the matching network to achieve further optimized design; and carrying out ESD testing to obtain the key parameter of the protection level. The method can accurately extract the device characteristics without constructing the complex numerical model, has higher accuracy and universality, and is suitable for the applicability evaluation and design optimization of the ESD protection device in a high-frequency circuit.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, relates to the electrostatic ESD protection optimization of radio frequency integrated circuits (RFICs), and can be used in the design of radio frequency integrated circuits. Background technique [0002] With the continuous shrinking of the feature size of CMOS integrated circuits and the increase of operating frequency, the problem of ESD protection of radio frequency integrated circuits has become more and more serious. The protection level is not high and there is no unified method. The design is time-consuming and the effect is not good. Since the integrated circuit RFIC has a lot of integrated content, including radio frequency front-end circuits, digital storage circuits, control circuits and other non-radio frequency circuits, and the designed circuits are unpredictable, it often depends on design experience to choose among multiple solutions , In addition, because the tape-ou...

AI Technical Summary

Problems solved by technology

[0003] (1) There are complex interactive effects between the ESD protection circuit and the protected core circuit

First of all, the performance of the ESD protection circuit will be affected by the surrounding environment. Parasitic devices in the area around the ESD protection circuit or inside the core circuit may act as parasitic ESD discharge channels. Since they are not designed for ESD protection, the discharge of ESD through these parasitic discharge channels will cause the failure of the integrated circuit, so an effective ESD protection circuit alone cannot guarantee that it will still be effective after being combined with the chip

Secondly, the ESD protection circuit will introduce some parasitic effects, such as parasitic capacitance, noise, etc. These parasitic effects may affect the performance of the core circuit, especially for high-speed, high-density mixed-signal circuits and radio frequency integrated circuits, the ESD protection circuit has a great impact on the core The impact of circuit performance is greater, and this problem will become more serious as process technology develops

[0004] (2) ESD protection circuit design lacks the support of high-current ESD protection device models and computer-aided design EDA tools

Therefore, the current design of ESD protection circuits mainly relies on tape-out verification to accumulate experience, and the cost is very high;

[0005] (3) The ESD protection circuit is non-portable. The performance of the ESD protection circuit is related to the process, size, and protected core circuit of the RFIC. Any changes in the process, layout shape, or core circuit to be protected will affect the original effective ESD. protection circuits may no longer be effective

However, there will be a large error in this way, and many parasitic effects will be ignored, resulting in a low level of ESD protection in the design or a serious deterioration in the performance of the core circuit.

On the one hand, the ESD protection circuit cannot simply be regarded as an ideal capacitor or a combination of resistor, inductor and capacitor RLC. Due to the many parasitic effects of the device, such an equivalent may not be accurate enough; secondly, at high frequencies, the parasitic capacitance of the ESD protection device or The inductance is not a constant, but is related to frequency, and slight changes in these parameters may cause a significant decrease in the performance of the designed core circuit; finally, in order to obtain a better matching effect, multi-level distribution is often used in higher frequency occasions Type matching network requires changing a large-sized single ESD protection device into a combination of multiple small-area devices, which makes the original equivalent method even more inaccurate

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