Method for manufacturing wafer-level patch panel

Abstract

The invention relates to a method for manufacturing a wafer-level patch panel, belonging to the technical field of integrated circuit or discrete device package. The method comprises the following steps of: taking a carrier wafer; sputtering or chemically plating a metal conductive layer on the carrier wafer; forming a mask graphic opening on the metal conductive layer; filling metal in the mask graphic opening; forming a metal cylinder array on the surface of the carrier wafer; filling the metal cylinder array of the whole carrier wafer with a substrate material of the patch panel to form a wafer with the metal cylinder array; separating the wafer from the carrier wafer; corroding the metal conductive layer on the wafer; and forming metal re-wiring graphs on the two surfaces of the wafer, and protecting the metal re-wiring graphs and forming metal re-wiring protection layers and opening graphs. Through the method for manufacturing the wafer-level patch panel, disclosed by the invention, the difficulty and the cost of the process can be greatly reduced, and the scale production of a high-density patch panel process can be achieved.

Description

technical field [0001] The invention relates to a method for preparing a wafer-level adapter board. It belongs to the technical field of packaging of integrated circuits or discrete devices. Background technique [0002] In recent years, with the rapid development of electronic packaging technology, some new packaging forms continue to emerge. Such as wafer-based wafer-level chip size packaging, three-dimensional stack packaging technology and flip-chip packaging technology. The emergence of these new packaging technologies not only improves the performance of the chip, but also greatly saves the size and volume of the package. [0003] Limited by chip size and reliable performance, the application range of wafer-level packaging technology is still limited to some low-pin-count products. In the three-dimensional stacking technology, although wire bonding can achieve multi-layer stacking, the application of high-speed signal transmission modules is limited by the length an...

AI Technical Summary

Problems solved by technology

[0003] Limited by chip size and reliability, the application range of wafer-level packaging technology is still limited to some low-pin-count products

In the three-dimensional stacking technology, although wire bonding can achieve multi-layer stacking, the application of high-speed signal transmission modules is limited by the length and diameter of the wires, so the use of large areas is still in flash memory, smart cards, radio frequency identification, etc.

[0008] 1) Through-hole formation, the usual way of forming through-holes is to use deep reactive ion etching, so the formation efficiency is low, and due to the control factors of the etching process, the formed through-hole wall has a scallop structure;

[0009] 2) Difficulty in deposition of dielectric layer

In order to ensure the insulation between silicon and the through-hole metal, a dielectric layer needs to be deposited on the through-hole wall, but the deposition of the dielectric layer is very difficult due to the extremely small size of the through-hole;

[0010] 3) It is difficult to fill the through hole metal

Since the metal filling of the through hole is to pre-deposit the seed layer metal in the through hole, and then use the electroplating process, it is difficult to avoid the void defect in the through hole (the growth characteristic of the electroplated metal) in this way.

[0011] Based on the above three reasons, silicon-based interposer technology using TSV technology does not yet have mass production capacity

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