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Method for removing photoinduced resist layer on semiconductor device structure

A photoresist layer and device structure technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem of affecting the electrical performance of semiconductor devices, failing to meet mass production, and thinning of germanium-silicon stress layer, etc. problems, to achieve the effect of improving the overall electrical performance, shortening the production cycle, and improving production efficiency

Active Publication Date: 2014-06-25
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Afterwards, strong sulfuric acid H is usually used 2 SO 4 and hydrogen peroxide H 2 o 2 A mixed solution of a mixed solution to completely remove residues, because most inorganic materials do not react with plasma to generate volatile substances, so they can only be removed by wet degumming process
However, since the SiGe material is more easily oxidized than the Si material, the O 2 or O 2 / H 2 O is used as an ashing gas to remove the photoresist layer, which will oxidize the silicon germanium material to SiO 2 , while the generated SiO 2 It is easy to be removed in the subsequent wet deglue process, resulting in the thinning of the silicon germanium stress layer and the inability to apply appropriate stress to the channel region of the PMOS structure, thus affecting the overall electrical performance of the final semiconductor device
If using N 2 and 3%~5%H 2 The mixed gas is used as an ashing gas to remove the photoresist layer, and the ashing process speed is too slow to meet the requirements of mass production

Method used

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  • Method for removing photoinduced resist layer on semiconductor device structure
  • Method for removing photoinduced resist layer on semiconductor device structure
  • Method for removing photoinduced resist layer on semiconductor device structure

Examples

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no. 1 example

[0034] figure 1is a flowchart 100 illustrating a method for removing a photoresist layer on a semiconductor device structure according to a first embodiment of the present invention.

[0035] like figure 1 As shown in , firstly, in step S101, the photoresist layer on the semiconductor device structure is ashed with a first ashing gas in a plasma ashing treatment chamber. Wherein, the first ashing gas contains N 2 and H 2 , but does not contain O 2 , and the H in the first ashing gas 2 The volume percentage is about 3% to 5%, and preferably 4%. In addition, the first ashing gas may also include other inert gases, such as He, Ar, etc., for diluting it. The first ashing gas facilitates removal of hard skin formed by photoresist and implanted ions during ion implantation. In this step, the flow rate of the first ashing gas is about 1000-20000 sccm, where sccm is the flow rate of 1 cubic centimeter per minute (1 ml / min) under standard conditions, ie, 1 atmosphere pressure an...

no. 2 example

[0039] figure 2 is a flowchart 200 illustrating a method for removing a photoresist layer on a semiconductor device structure according to a second embodiment of the present invention.

[0040] like figure 2 As shown in , steps S201 and S202 are respectively related to figure 1 Steps S101 and S102 in are the same as figure 1 The method shown in differs in that, figure 2 The method shown in also includes step S203. In step S203, pass O into the plasma ashing treatment chamber 2 is purged, and O 2 The flow rate is 500-5000 sccm. Wherein, the purging duration is longer than 1 second and shorter than 10 seconds, and it is carried out under the conditions of a pressure of 0.5-5T, a power of 1000-5000W and a temperature of 100-200°C. Limit the purging time to less than 10 seconds and control the temperature in the plasma ashing treatment chamber in the range of 100-200°C, in order to prevent the germanium-silicon stress layer from being accelerated due to too long purging ...

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Abstract

The invention provides a method for removing a photoinduced resist layer on a semiconductor device structure. The method comprises the following steps of: (1) using first ashing gas in a plasma ashing treatment cavity to carry out ashing on the photoinduced resist layer on the semiconductor device structure; and (2) using second ashing gas in the plasma ashing treatment cavity to carry out ashing on the photoinduced resist layer on the semiconductor device structure, wherein the first ashing gas and the second ashing gas contain N2 and H2 without containing O2, and the volume percentage of H2 in the first ashing gas is less than that of H2 in the second ashing gas. According to the method provided by the invention, the damage to the silicon-germanium material in the process of adopting the plasma ashing process to remove the photoinduced resist layer can be prevented, so that the whole electric performance of the semiconductor device is improved, the production cycle can be shortened and the production efficiency is improved.

Description

technical field [0001] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for removing a photoresist layer on a semiconductor device structure. Background technique [0002] At present, the main factor affecting the performance of field effect transistors is the mobility of carriers, where the mobility of carriers will affect the magnitude of the current in the channel. The reduction in carrier mobility in a field effect transistor not only reduces the switching speed of the transistor, but also reduces the difference in resistance between on and off. Therefore, in the development of complementary metal-oxide-semiconductor field-effect transistors (CMOSFET, CMOS for short), effectively improving carrier mobility has always been one of the key points in transistor structure design. [0003] Conventionally, in the manufacturing technology of CMOS devices, PMOS devices and NMOS devices are processed separately. T...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/311H01L21/336
Inventor 韩秋华孟晓莹
Owner SEMICON MFG INT (SHANGHAI) CORP