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Bump packaging structure and bump packaging method

A packaging method and packaging structure technology, which is applied to the assembly of printed circuits with electrical components, printed circuits connected with non-printed electrical components, electrical components, etc., can solve the problem of low yield rate of bump packaging structure, increased packaging difficulty, Problems such as the reduction of the bump pitch can achieve the effects of high packaging quality, reduced packaging difficulty, and improved packaging quality

Active Publication Date: 2016-04-13
CHINA WAFER LEVEL CSP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, as the number of electrodes of the chip to be packaged continues to increase, the distance between the bumps after packaging continues to decrease. The more commonly used bump soldering material is tin-lead. Prone to excessive deformation, leading to bump-to-bump shorts
[0009] And with the further development of the chip to be packaged, the area of ​​the bump is also reduced, so that the contact area between the bump and the electrode on the PCB board is reduced, the difficulty of packaging is increased, and the yield of the packaged bump packaging structure is low.

Method used

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  • Bump packaging structure and bump packaging method
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  • Bump packaging structure and bump packaging method

Examples

Experimental program
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Effect test

no. 1 example

[0063] The bump packaging method of the present invention will be described in detail below in conjunction with the first embodiment, please refer to Figure 5 , including the following steps:

[0064] Step S101, providing a substrate to be packaged, the surface of the substrate to be packaged has a pad, the surface of the substrate to be packaged has a passivation layer, and the passivation layer covers part of the surface of the pad;

[0065] Step S102, forming a bump on the surface of the pad;

[0066] Step S103, forming an anisotropic conductive adhesive layer covering the bump on the surface of the passivation layer;

[0067] Step S104, providing a PCB board, the PCB board has electrodes protruding from the surface of the PCB board, and the positions of the electrodes correspond to the positions of the bumps;

[0068] Step S105, pressing the PCB board to the substrate to be packaged, so that the bump is directly opposite to the electrode and the surface of the PCB board...

example 1

[0077] A metal film covering the welding pad 101 and the passivation layer 102 is formed by a physical vapor deposition process; a photoresist pattern is formed on the surface of the metal film, and the photoresist pattern covers the metal film corresponding to the welding pad 101 ; using the photoresist pattern as a mask, etching the metal film until the passivation layer 102 is exposed to form bumps 110;

[0078] In this example, the metal film may be a single film layer or a multi-layer stacked structure.

example 2

[0080] A metal plate is provided, and the metal plate is bonded to the substrate to be packaged 100; a photoresist pattern is formed on the surface of the metal plate, and the photoresist pattern covers the metal plate corresponding to the welding pad 101; The photoresist pattern is a mask, and the metal plate is etched by wet etching or dry etching until the passivation layer 102 is exposed to form bumps 110 .

[0081] In this example, the metal plate may be a multi-layer stack or a single layer, and the material of the metal plate may be metal or alloy.

[0082] Please refer to Figure 8 , forming an anisotropic conductive adhesive layer 120 covering the bump 110 on the surface of the passivation layer 102 .

[0083] The surface of the anisotropic conductive adhesive layer 120 is higher than the surface of the bump 110 .

[0084] The material of the anisotropic conductive adhesive layer 120 is anisotropic conductive film (AnisotropicConductiveFilm, ACF), which has the char...

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Abstract

The invention discloses a bulge encapsulating structure and a bulge encapsulating method, wherein the bulge encapsulating method comprises the following steps: providing a to-be-encapsulated substrate, wherein the surface of the to-be-encapsulated substrate is provided with a welding pad, and the surface of the welding pad is provided with bulges; forming an anisotropic conductive adhesive layer (for covering the bulges) on the surface of the to-be-encapsulated substrate; providing a PCB (Printed circuit board) board, wherein the PCB board is provided with electrodes protruded from the surface of the PCB board, and the positions of the electrodes are corresponding to the positions of the bulges; and carrying out press fit on the PCB board and the to-be-encapsulated substrate, so that the positions of the electrodes are dead against the positions of the bulges, and the surface of the PCB board is contacted with the surface of the anisotropic conductive adhesive layer, wherein a pressure perpendicular to the surface of the to-be-encapsulated substrate is exerted on the anisotropic conductive adhesive layer between the bulges and the electrodes. The bulge encapsulating method disclosed by the embodiment of the invention is simple in process, and the bulge encapsulating structure disclosed by the embodiment of the invention is high in encapsulating quality.

Description

technical field [0001] The invention relates to the field of chip packaging, in particular to a bump packaging structure and a bump packaging method for wafer level packaging. Background technique [0002] With the development of portable and high-performance microelectronic products in the direction of shortness, smallness, lightness, and thinning, the traditional wire bonding method (Wire Bonding) as a packaging technology for combining chips with various substrates can no longer meet the needs of current consumer electronics products. , The replaced bump packaging has become the key technology of wafer level packaging. [0003] Bump packaging is widely used in the packaging of driver chips, image sensor chips, and RFID of flat-panel displays. The existing bump packaging process includes the following steps: [0004] Please refer to figure 1 , providing a chip to be packaged, the chip to be packaged comprising: a substrate 10, a pad 12 positioned on the surface of the s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/603H01L23/488H05K3/34H05K1/18
CPCH01L2224/73204H01L2924/07811
Inventor 王之奇王宥军俞国庆王琦喻琼王蔚
Owner CHINA WAFER LEVEL CSP