Clock generating method and clock generating circuit for CMOS (complementary metal oxide semiconductor) without crystal oscillator

Abstract

The invention relates to a clock generating method and a clock generating circuit for a CMOS (complementary metal oxide semiconductor) without a crystal oscillator. The clock generating method includes: generating high-frequency sine oscillation signals by a digital-control oscillator; converting the high-frequency sine oscillation signals into square-wave signals output in single-end mode; underclocking the square-wave signals to obtain clock signals of preset frequency according to preset fractional frequency; regulating duty ratio of the clock signals so that the duty ratio of the clock signals can meet the requirement of preset duty ratio of clock, and outputting the clock signals, wherein a variable capacitor array in the digital-control oscillator is controlled by frequency locking control information. A method for setting the frequency locking control information includes: generating frequency control information according to frequency difference between output signals of an external crystal oscillator and the clock signals underclocked. By the clock generating method, the clock generating circuit can be smaller in size and lower in power consumption, low-cost CMOS technology can be realized in chips, and accordingly, integrity and stability of the system are improved, system realizing cost and power consumption are reduced.

Description

technical field [0001] The invention relates to clock generation technology, in particular to a crystal-less CMOS clock generation method and a crystal-less CMOS clock generation circuit. Background technique [0002] The clock signal is very important for many electronic products, and various components in the electronic product can work together under the action of the clock signal. [0003] Currently, clock generation methods mainly include the following three types: [0004] Method 1: A clock signal is generated by using a phase locked loop (Phase Lock Loop, PLL) frequency synthesizer. A specific example of a PLL frequency synthesizer is figure 1 shown. [0005] figure 1 The phase-locked loop frequency synthesizer mainly includes: crystal oscillator, frequency divider (including figure 1 programmable frequency divider), frequency and phase detectors, charge pumps, low-pass filters, and voltage-controlled oscillators. A phase frequency detector compares the phases o...

AI Technical Summary

Problems solved by technology

[0010] The inventor found in the process of realizing the present invention that: the above-mentioned method 1 has the problems of off-chip implementation and high power consumption; specifically, with the development of large-scale integrated circuit technology, the integration degree of the chip is getting higher and higher, and the area of ​​the chip is getting higher and higher. The smaller the crystal oscillator is, the off-chip implementation is usually used; however, the off-chip implementation will affect the area, cost and reliability of the system; in addition, the power consumption of the crystal oscillator and its additional circuits is not low, thus becoming a

Images