Dual polycrystalline strain SiGe plane bipolar complementary metal oxide semiconductor (BiCMOS) integrated device and preparation method

An integrated device and double polycrystalline technology, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of reducing the precision of lithography, unsatisfactory lithography technology, and difficulty in meeting design.

Inactive Publication Date: 2012-10-17
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For example, when the feature size is less than 100nm, due to problems such as tunneling leakage current and reliability, the traditional gate dielectric material SiO 2 Unable to meet the requirements of low power consumption; the short channel effect and narrow channel effect of nanometer devices are becoming more and more obvious, which seriously affects the device performance; traditional lithography technology cannot meet the shrinking lithography precision
Therefore, traditional Si-based process devices are increasingly difficult to meet the needs of design

Method used

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  • Dual polycrystalline strain SiGe plane bipolar complementary metal oxide semiconductor (BiCMOS) integrated device and preparation method

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Experimental program
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Embodiment 1

[0120] Embodiment 1: Preparation of dual polycrystalline strained SiGe planar BiCMOS integrated devices and circuits with a channel length of 22 nm, the specific steps are as follows:

[0121] Step 1, SOI substrate material preparation.

[0122] (1a) Select N-type doping concentration as 1×10 15 cm -3 The surface of the Si wafer is oxidized, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0123] (1b) Select the N-type doping concentration as 1×10 15 cm -3 The surface of the Si wafer is oxidized, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;

[0124] (1c) Use chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of the base material after hydrogen injection;

[0125] (1d) Place the polished lower layer and upper layer of the base material surface oxide layer relatively closely, and...

Embodiment 2

[0186] Embodiment 2: Preparation of a dual polycrystalline strained SiGe planar BiCMOS integrated device and circuit with a channel length of 130 nm, the specific steps are as follows:

[0187] Step 1, SOI substrate material preparation.

[0188] (1a) Select the N-type doping concentration to be 3×10 15 cm -3 The surface of the Si wafer is oxidized, and the thickness of the oxide layer is 0.7μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0189] (1b) Choose N-type doping concentration as 3×10 15 cm -3 The surface of the Si wafer is oxidized, and the thickness of the oxide layer is 0.7μm, as the base material of the lower layer;

[0190] (1c) Use chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of the base material after hydrogen injection;

[0191] (1d) Place the polished lower layer and upper layer of the substrate material surface oxide layer relatively close, and plac...

Embodiment 3

[0252] Embodiment 3: Preparation of a dual polycrystalline strained SiGe planar BiCMOS integrated device and circuit with a channel length of 350 nm, the specific steps are as follows:

[0253] Step 1, SOI substrate material preparation.

[0254] (1a) Choose N-type doping concentration as 5×10 15 cm -3 The surface of the Si wafer is oxidized, and the thickness of the oxide layer is 0.5μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0255] (1b) Select N-type doping concentration as 5×10 15 cm -3 The surface of the Si wafer is oxidized, and the thickness of the oxide layer is 0.5μm, as the base material of the lower layer;

[0256] (1c) Use chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper active layer matrix material after hydrogen injection;

[0257] (1d) Place the polished lower layer and upper layer of the substrate material surface oxide layer relatively closely, and place i...

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Abstract

The invention discloses a method for preparing a dual polycrystalline strain SiGe plane bipolar complementary metal oxide semiconductor (BiCMOS) integrated device. The method comprises the following steps of: preparing a silicon-on-insulator (SOI) substrate, etching a bipolar device area on the substrate, preparing a dual polycrystalline SiGe heterojunction bipolar transistor (HBT) device in the area by using a chemical vapor deposition (CVD) method and a self-aligning process, photo-etching a metal oxide semiconductor (MOS) active area, continuously growing a Si buffer layer, a strain SiGe layer and an intrinsic layer in the area, respectively forming active areas of n-channel metal oxide semiconductor (NMOS) and p-channel metal oxide semiconductor (PMOS) devices, depositing SiO2 and polycrystalline silicon in the active areas of the NMOS and PMOS devices, etching a pseudo grid with the length of 22 to 350 nanometers, forming a light doped drain (LDD) and a source drain of the NMOS and PMOS devices by adopting the self-aligning process, then removing the pseudo grid, forming grid dielectric lanthanum oxide (La2O3) and metallic tungsten (W) for forming a grid, metalizing, photo-etching leads, and thus forming a BiCMOS integrated circuit. The self-aligning process is adopted in the preparation method, and the LDD structure is adopted in the MOS structure, so that influence of hot carriers on performance of the device is efficiently inhibited, and the reliability of the device is improved.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a dual polycrystalline strained SiGe planar BiCMOS integrated device and a preparation method. Background technique [0002] Semiconductor integrated circuit technology is the core technology of the high-tech and information industry. It has become an important indicator of a country's scientific and technological level, comprehensive national strength, and national defense strength. Microelectronics technology represented by integrated circuits is the key to semiconductor technology. The semiconductor industry is the country's basic industry. The reason why it has developed so fast is not only related to its huge contribution to economic development, but also to its wide range of applications. [0003] Gordon Moore, one of the founders of Intel, proposed "Moore's Law" in 1965. The theorem states that the number of transistors on an integrated circu...

Claims

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Application Information

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IPC IPC(8): H01L27/06H01L21/8249
Inventor 胡辉勇张鹤鸣宋建军宣荣喜舒斌周春宇王斌郝跃
Owner XIDIAN UNIV
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