Method for achieving controller area network (CAN) bus network nodes

Abstract

The invention discloses a method for achieving controller area network (CAN) bus network nodes. In a field programmable gate array (FPGA), a soft core driver connected with a soft core bus is adopted. The soft core driver is connected with a CAN drive software processor through a processor bus, and a CAN interface chip completing transmission of a single-ended signal to a CAN interface is connected between a CAN soft core controller end and a CAN bus. An interrupt request signal of a CAN soft core controller in the FPGA is transmitted to a processor interrupt tube pin connected behind a reverser through the reverser. The soft core controller transmits a soft core chip select signal generated by combining a 31st -bit to 8th -bit signal output by the CAN drive software processor and a chip select signal output by the CAN drive software processor into the CAN soft core controller. The soft core driver converts a processor bus interface into a soft core bus interface, and then transmission and receiving of CAN data of the CAN bus network nodes can be achieved through the CAN soft core controller. The method is simple in structure, flexible in design and suitable for a system composed of a processor and a field programmable gate array chip.

Description

technical field [0001] The invention relates to a method for realizing a CAN bus network node mainly by using a programmable logic array (FPGA) device and a CPU-based processor. Background technique [0002] Because the CAN bus has excellent performance and high reliability, the mature technology has been widely used in airborne equipment as a module control bus. The CAN communication node design in the prior art generally adopts the following schemes: [0003] 1. The CAN network node is realized by using a single-chip microcomputer with CAN interface function. [0004] 2. Use single-chip microcomputer, digital signal processor (DSP), FPGA and CAN bus controller chip to realize CAN network nodes. Commonly used bus controller chips include SJA1000, MCP2515 and so on. [0005] 3. On the FPGA, the CAN bus soft core is used to realize the CAN bus controller, and the logic code is written in the hardware design language to control the soft core to realize the CAN network node. ...

AI Technical Summary

Problems solved by technology

The adoption of scheme 1 requires the addition of a single-chip microcomputer chip; the adoption of scheme 2 requires the addition of additional bus controller chips; the scheme 3 does not require the addition of additional chips, but the method of using hardware description language to control the soft core in the FPGA is complex in design and inflexible in modification

Solution 4 has the advantages of Solution 3, but the disadvantage is that it needs to embed a CPU, which consumes more logic resources, and also increases power consumption and design complexity.

Option 1 and 2 need to increase the chip, which increases the size, power consumption, and weight

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