Compensation method for increase of amplification times of direct current caused by thinning of germanium-silicon edge

Abstract

The invention discloses a compensation method for increase of amplification times of direct current caused by thinning of a germanium-silicon edge. A germanium-silicon layer is formed on an epitaxial layer which is formed on a silicon substrate, a medium film is deposited on the germanium-silicon layer, and an emitter window is formed by etching the medium film to deposit emitter polysilicon. The compensation method includes following steps: performing ion implantation for the first time; plating a layer of negative optical glue, performing chip edge exposure of 8-12mm, removing photoresistance in the middle of a chip by development; and performing ion implantation for the second time. The photoresistance in the middle of the chip is removed by adopting chip edge exposure development, and an edge is covered by the photoresistance, so that the second ion implantation cannot enter the edge, doping concentration of the edge emitter polysilicon is lowered, base diffusion current increases, and ascending of collector current can be effectively compensated; and distribution of in-plane direct current amplification times of a whole single crystal silicon piece is tighter. The compensation method for increase of amplification times of direct current caused by thinning of the germanium-silicon edge is simple in process and remarkably improved in product yield.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a method for compensating the increase in collector current caused by edge thinning when germanium and silicon are grown on a non-patterned optical sheet in the manufacturing process of germanium-silicon heterojunction bipolar triode power devices The method of multiplying the dc current method caused by it. Background technique [0002] For radio frequency applications in the 1G Hz range, germanium-silicon heterojunction bipolar transistor devices generally adopt the method of leading out the collector on the back, that is, low N-doped epitaxial growth is performed on the N-type heavily doped substrate to form the collector region. Its advantage is that the process is simple, and the mask layer can be reduced by half compared with the traditional process. The disadvantage is that when silicon germanium is grown on the optical wafer, the thickness of the silicon g...

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Problems solved by technology

Its advantage is that the process is simple, and the mask layer can be reduced by half compared with the traditional process. The disadvantage is that when silicon germanium is grown on the optical wafer, the thickness of the silicon germanium epitaxial layer will drop sharply from the edge of the wafer about 12mm. The thickness of each layer of the silicon germanium epitaxial layer will be lower than the center, and the thickness difference can reach up to 20%. This is due to the combined effect of the design of the heating method of the epitaxial equipment and the heat conduction of the light sheet.

Since the collector current is inversely proportional to the product of the doping concentration and thickness of the germanium-silicon epitaxial layer, in this way, if the same doping concentration of the emitter polysilicon is used in the entire single-crystal silicon wafer, a key parameter of the device ——The distribution of DC current magnification will be very wide, and even the upper limit will be exceeded within 8 mm from the edge, resulting in a drop in yield

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