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Selective emitter solar cell with front electrode main grid line isolated from silicon substrate and preparation method thereof

A technology of solar cells and busbars, applied in the field of solar cells, can solve the problems of large metal-semiconductor contact recombination, high electron-hole recombination speed, limited ability to collect effective electrons, etc., and achieves low manufacturing cost and improved open circuit voltage. , the effect of reducing the proportion

Active Publication Date: 2016-03-02
江苏润阳光伏科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Conventional selective emitter cells use the local re-doped structure at the bottom of the front electrode grid line to obtain solar cells with good optical and electrical properties, but the local re-doped area accounts for about 6% to 10% of the front surface area of ​​the silicon wafer. The line-localized heavily doped region accounts for more than 50% of the heavily doped region, and the electron-hole recombination velocity in these heavily doped regions is very high
At the same time, the metal-semiconductor contact formed by the silver paste of the busbar and the silicon substrate recombines greatly, and the bottom area of ​​the busbar is blocked by the gate line, generating few electron-hole pairs, which has limited ability to collect effective electrons

Method used

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  • Selective emitter solar cell with front electrode main grid line isolated from silicon substrate and preparation method thereof
  • Selective emitter solar cell with front electrode main grid line isolated from silicon substrate and preparation method thereof
  • Selective emitter solar cell with front electrode main grid line isolated from silicon substrate and preparation method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0050] ⑴ if figure 1As shown, the silicon wafer substrate 1 is placed in a high-temperature diffusion furnace, and POCl3 is used as a phosphorus source, and an n+ layer 2 is formed on both sides of the silicon wafer through high-temperature diffusion and phosphorus doping. The sheet resistance of the n+ layer 2 is 90-100Ω / □.

[0051] ⑵ if figure 2 As shown, the n++ layer is formed by local heavy doping of phosphorous sources at the bottom of the thin gate line pattern on the front surface of the silicon wafer, and the n+ layer 3 is still at the bottom of the main gate line pattern, and the sheet resistance of the n++ layer 3 is 20-30Ω / □.

[0052] ⑶ if image 3 As shown, the n+ layer 2 on the back of the silicon wafer substrate 1 is removed by single-sided etching equipment using a HF / HNO3 mixed solution, wherein the concentration of the HF solution is 49%, the concentration of the HNO3 solution is 69%, and the volume ratio of the HF solution to the HNO3 solution is 1 :3.

...

Embodiment 2

[0060] ⑴ if figure 1 As shown, the silicon substrate 1 is placed in a high-temperature diffusion furnace, and POCl3 is used as a phosphorus source, and n+ layers 2 are formed on both sides of the silicon wafer through high-temperature diffusion and doping of phosphorus. The sheet resistance of the n+ layer 2 is 100-110Ω / □.

[0061] ⑵ if figure 2 As shown, the n++ layer 3 is formed by local heavy doping of phosphorous sources at the bottom of the fine gate line pattern on the front surface of the silicon wafer, and the n+ layer 2 is still at the bottom of the main gate line pattern, and the square resistance of the n++ layer 3 is 30-40Ω / □.

[0062] ⑶ if image 3 Shown adopts HF / HNO mixed solution to remove the n+ layer 2 on the back side of silicon wafer substrate 1 by single-sided etching equipment, wherein the concentration of HF solution is 49%, the concentration of HNO solution is 69%, and the volume ratio of HF solution and HNO solution is 1: 3.

[0063] ⑷ such as Fi...

Embodiment 3

[0070] ⑴ if figure 1 As shown, the silicon wafer substrate 1 is placed in a high-temperature diffusion furnace, and POCl3 is used as a phosphorus source, and an n+ layer 2 is formed on both sides of the silicon wafer through high-temperature diffusion and phosphorus doping. The sheet resistance of the n+ layer 2 is 110-120Ω / □.

[0071] ⑵ if figure 2 As shown, the n++ layer is locally re-doped with phosphorous sources at the bottom of the thin gate line pattern on the front surface of the silicon wafer, the bottom of the main gate line pattern is still n+ layer 2, and the sheet resistance of n++ layer 3 is 40-50Ω / □.

[0072] ⑶ if image 3 As shown, the n+ layer 2 on the back side of the silicon wafer substrate 1 is removed by single-side etching equipment using NaOH solution, wherein the concentration of NaOH solution is 20%.

[0073] ⑷ such as Figure 5 As shown, a silicon nitride antireflection film layer 4 is plated on the front surface of the silicon wafer substrate 1 b...

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Abstract

The invention discloses a front electrode main grid line and silicon substrate isolated selective emitter solar battery and a preparation method thereof. The selective emitter solar battery comprises a silicon wafer with a p size slice substrate, an expanding phosphorus n+ layer, an n++ layer which is positioned at the bottom portion of a slim grid line pattern, a silicon nitride reducing membrane layer, a silicon nitride isolating layer and a silver front electrode are successively arranged on the front surface of the silicon wafer. A main grid line pattern and the slim grid line pattern which are positioned at the bottom portion are arranged on the silver front electrode, an aluminum-back surface field and an aluminum-back electrode are successively on the back surface of the silicon wafer. By adopting the front electrode main grid line and the silicon substrate isolating technology, the front electrode main grid line and silicon substrate isolated selective emitter solar battery and the preparation method thereof have the advantages of effectively reducing heavy doped area ratio of the front surface, lowering a flaw composition of the grid line bottom portion area, meanwhile increasing a silicon nitride passivation area of the silicon wafer front surface, avoiding a composition caused by contact of the main grid line metal silver and the ohm of the silicon substrate, and effectively improving an open circuit voltage, short circuit current and battery transforming efficiency. The front electrode main grid line and silicon substrate isolated selective emitter solar battery and the preparation method thereof further have the advantages of being simple in technical process, lower in manufacturing cost, suitable for large scale production, thereby having an enormous market prospect.

Description

technical field [0001] The invention belongs to the technical field of solar cells, and in particular relates to a selective emitter solar cell with a front electrode main grid line isolated from a silicon substrate and a preparation method thereof. Background technique [0002] With the innovation of solar cell technology and the continuous improvement of solar cell conversion efficiency, the production cost of solar cells and components has been greatly reduced, and the photovoltaic industry has developed rapidly with the support of policies from governments of various countries. In order to achieve higher conversion efficiency and lower production costs, researchers have proposed many new processes, new methods and new structures through theory and practice. Selective emitter cell structure, as one of the high-efficiency cell structures, has been applied in actual production by most solar cell companies. The selective emitter cell adopts the technology of heavy doping at...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L31/0224H01L31/0216H01L31/068H01L31/18
CPCY02E10/547Y02P70/50
Inventor 沈辉刘家敬刘斌辉李力李明华陈思铭
Owner 江苏润阳光伏科技有限公司
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