Selective emitter solar cell with front electrode main grid line isolated from silicon substrate and preparation method thereof
A technology of solar cells and busbars, applied in the field of solar cells, can solve the problems of large metal-semiconductor contact recombination, high electron-hole recombination speed, limited ability to collect effective electrons, etc., and achieves low manufacturing cost and improved open circuit voltage. , the effect of reducing the proportion
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Embodiment 1
[0050] ⑴ if figure 1As shown, the silicon wafer substrate 1 is placed in a high-temperature diffusion furnace, and POCl3 is used as a phosphorus source, and an n+ layer 2 is formed on both sides of the silicon wafer through high-temperature diffusion and phosphorus doping. The sheet resistance of the n+ layer 2 is 90-100Ω / □.
[0051] ⑵ if figure 2 As shown, the n++ layer is formed by local heavy doping of phosphorous sources at the bottom of the thin gate line pattern on the front surface of the silicon wafer, and the n+ layer 3 is still at the bottom of the main gate line pattern, and the sheet resistance of the n++ layer 3 is 20-30Ω / □.
[0052] ⑶ if image 3 As shown, the n+ layer 2 on the back of the silicon wafer substrate 1 is removed by single-sided etching equipment using a HF / HNO3 mixed solution, wherein the concentration of the HF solution is 49%, the concentration of the HNO3 solution is 69%, and the volume ratio of the HF solution to the HNO3 solution is 1 :3.
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Embodiment 2
[0060] ⑴ if figure 1 As shown, the silicon substrate 1 is placed in a high-temperature diffusion furnace, and POCl3 is used as a phosphorus source, and n+ layers 2 are formed on both sides of the silicon wafer through high-temperature diffusion and doping of phosphorus. The sheet resistance of the n+ layer 2 is 100-110Ω / □.
[0061] ⑵ if figure 2 As shown, the n++ layer 3 is formed by local heavy doping of phosphorous sources at the bottom of the fine gate line pattern on the front surface of the silicon wafer, and the n+ layer 2 is still at the bottom of the main gate line pattern, and the square resistance of the n++ layer 3 is 30-40Ω / □.
[0062] ⑶ if image 3 Shown adopts HF / HNO mixed solution to remove the n+ layer 2 on the back side of silicon wafer substrate 1 by single-sided etching equipment, wherein the concentration of HF solution is 49%, the concentration of HNO solution is 69%, and the volume ratio of HF solution and HNO solution is 1: 3.
[0063] ⑷ such as Fi...
Embodiment 3
[0070] ⑴ if figure 1 As shown, the silicon wafer substrate 1 is placed in a high-temperature diffusion furnace, and POCl3 is used as a phosphorus source, and an n+ layer 2 is formed on both sides of the silicon wafer through high-temperature diffusion and phosphorus doping. The sheet resistance of the n+ layer 2 is 110-120Ω / □.
[0071] ⑵ if figure 2 As shown, the n++ layer is locally re-doped with phosphorous sources at the bottom of the thin gate line pattern on the front surface of the silicon wafer, the bottom of the main gate line pattern is still n+ layer 2, and the sheet resistance of n++ layer 3 is 40-50Ω / □.
[0072] ⑶ if image 3 As shown, the n+ layer 2 on the back side of the silicon wafer substrate 1 is removed by single-side etching equipment using NaOH solution, wherein the concentration of NaOH solution is 20%.
[0073] ⑷ such as Figure 5 As shown, a silicon nitride antireflection film layer 4 is plated on the front surface of the silicon wafer substrate 1 b...
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