Insulated gate transistor device and manufacturing technology method thereof

Abstract

The invention discloses an insulated gate transistor device and manufacturing technology method of the insulated gate transistor device. High-energy ions are filled into a P well region and an interface position of an N+ emitting electrode to from a layer of metal silicide. An ion mixing zone with high condensation is formed in a zone, connected with the emitting electrode, of a partial zone of the N+ emitting electrode (above the buried layer of the metal silicide) in a manner of filling the high-energy ions to accelerate instant heating processing. Thus, a low-resistance zone is formed and the buried layer of metal silicide and a superficial emitting electrode are connected. Compared with traditional technology, according to the manufacturing technology method of the insulated gate transistor device, machining technology of the insulated gate transistor device is simple, manufacturing cost is low, massive production of IGBT products is benefited. The IGBT devices with specific structures can effectively prevent latch-up from happening.

Description

technical field [0001] The invention belongs to the field of electronic technology, relates to a power semiconductor device, in particular to an insulated gate transistor device (IGBT) and a manufacturing process thereof for preventing the latch effect of the insulated gate transistor. Background technique [0002] Insulated Gate Transistor (hereinafter referred to as IGBT) is a new type of power semiconductor device with rapid development and wide application. [0003] like figure 1 As shown, the device structure of a traditional N-type IGBT includes a P+ semiconductor substrate 1, a layer of N- epitaxial layer 2 is grown on the P+ semiconductor substrate 1 by epitaxy, and then a P well region 3 and a P well region 3 are formed by ion implantation. N+ emitter 4. Next, a gate oxide layer 5 and polysilicon 6 are grown in the P well region 3 between the N+ emitter 4 and the N- epitaxial layer 2 as the gate of the field effect transistor, and the gate oxide layer 5 and polysi...

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Problems solved by technology

The limitation of this process is that the contact holes on the metal buried layer and the contact holes on the N+ need to be formed at the same time, that is to say, when the contact holes are etched, a part of the contact holes need to be etched to the surface of the single crystal silicon, while the other part of the contact holes need to be etched. Need to etch to the metal oxide surface, the current etching process in the semiconductor manufacturing industry is difficult to meet such requirements

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